Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. A display device (e.g., a liquid crystal display device and a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like may include a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, manufacture, or a composition (composition of matter).

BACKGROUND ART

As semiconductor thin films applicable to transistors, silicon-based semiconductor materials have been widely known, but oxide semiconductors have been attracting attention as alternative materials. Examples of oxide semiconductors include not only single-component metal oxides, such as indium oxide and zinc oxide, but also multi-component metal oxides. Among the multi-component metal oxides, in particular, an In—Ga—Zn oxide (hereinafter also referred to as IGZO) has been actively studied.

From studies on IGZO, in an oxide semiconductor, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are not single crystal nor amorphous, have been found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, a technique for forming a transistor using an oxide semiconductor having the CAAC structure is disclosed. Moreover, Non-Patent Documents 4 and 5 disclose that a fine crystal is included even in an oxide semiconductor which has lower crystallinity than an oxide semiconductor having the CAAC structure or the nc structure.

In addition, a transistor which includes IGZO as an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Documents 7 and 8).

REFERENCE Non-Patent Document

-   [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of     Technical Papers”, 2012, volume 43, issue 1, pp. 183-186 -   [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of     Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 -   [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13     Digest of Technical Papers”, 2013, pp. 151-154 -   [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid     State Science and Technology”, 2014, volume 3, issue 9, p.     Q3012-Q3022 -   [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014,     volume 64, issue 10, pp. 155-164 -   [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied     Physics”, 2012, volume 51, p. 021201-1-021201-7 -   [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI     Technology Digest of Technical Papers”, 2015, p. T216-T217 -   [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of     Technical Papers”, 2010, volume 41, issue 1, pp. 626-629

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide a semiconductor device with a high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long time. Another object of one embodiment of the present invention is to provide a semiconductor device capable of high-speed data writing. Another object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the descriptions of these objects do not disturb the existence of other objects. One embodiment of the present invention does not have to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention is a semiconductor device including a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with part of a top surface of the second oxide, part of a side surface of the second oxide, and part of a side surface of the third oxide, a third insulator over the second insulator, and a fourth insulator in contact with a top surface of the third oxide, a top surface of the first insulator, a top surface of the conductor, and a top surface of the third insulator; the second oxide includes a first region, a second region, a third region positioned between the first region and the second region, a fourth region positioned between the first region and the third region, and a fifth region positioned between the second region and the third region; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region; part of the third oxide and part of the first insulator are provided between a side surface of the conductor and a side surface of the third insulator; and the second insulator is in contact with the first region and the second region.

In the above, it is preferable that the conductor overlap with at least part of the first region and part of the second region. Furthermore, in the above, it is preferable that the semiconductor device include a fifth insulator in contact with a top surface of the second insulator and the fifth insulator is in contact with a bottom surface of the third insulator and the side surface of the third oxide.

In the above, it is preferable that the first region, the second region, the fourth region, and the fifth region contain one of phosphorus or boron. Furthermore, in the above, it is preferable that the first region and the second region contain phosphorus or boron more than the fourth region and the fifth region. Furthermore, it is preferable that the first region, the second region, the fourth region, and the fifth region contain more oxygen vacancies than the third region. Furthermore, it is preferable that the first region, the second region, the fourth region, and the fifth region contain more hydrogen than the third region.

Another embodiment of the present invention is a method for manufacturing a semiconductor device including steps of forming a first oxide and a second oxide over the first oxide, forming a first insulating film covering the first oxide and the second oxide, forming a first dummy gate over the first insulating film to overlap with the second oxide, adding a first dopant to the second oxide using the first dummy gate as a mask, forming a second dummy gate by removing part of the first dummy gate and exposing part of the second oxide from the second dummy gate, adding a second dopant to the second oxide using the second dummy gate as a mask, forming a second insulating film covering the first insulating film and the second dummy gate, forming a third insulating film over the second insulating film, removing part of the second insulating film and part of the third insulating film until a top portion of the second dummy gate is exposed, forming an opening by removing the second dummy gate, part of the second insulating film, and part of the first insulating film, forming a third oxide, a fourth insulating film, and a conductive film in this order to be embedded in the opening, and removing part of the third oxide, part of the fourth insulating film, and part of the conductive film until a top portion of the third insulating film is exposed.

In the above, it is preferable that phosphorus or boron is used for the first dopant and the second dopant. Furthermore, it is preferable that the addition amount of the first dopant be larger than the addition amount of the second dopant. Furthermore, it is preferable that an ion implantation method or an ion doping method be used for the addition of the first dopant and the second dopant. Furthermore, it is preferable that the first dummy gate contain carbon.

Furthermore, it is preferable that the second dummy gate be formed by ashing treatment using an oxygen radical.

Effect of the Invention

According to one embodiment of the present invention, a semiconductor device with a high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

Alternatively, a semiconductor device capable of retaining data for a long time can be provided. Alternatively, a semiconductor device capable of high-speed data writing can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device capable of reducing power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the descriptions of the effects do not disturb the existence of other effects. One embodiment of the present invention does not have to have all of these effects. Effects other than these will be apparent from the description of the specification, the drawings, the claims, and the like and effects other than these can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.

FIG. 2 A cross-sectional view of a semiconductor device according to one embodiment of the present invention.

FIG. 3 A cross-sectional view of a semiconductor device according to one embodiment of the present invention.

FIG. 4 A top view and cross-sectional views of a semiconductor device of one embodiment of the present invention.

FIG. 5 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 6 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 7 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 8 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 9 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 10 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 11 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 12 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 13 A top view and cross-sectional views showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 14 A top view and cross-sectional views showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 15 A top view and cross-sectional views of a semiconductor device of one embodiment of the present invention.

FIG. 16 A top view and cross-sectional views showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 17 A top view and cross-sectional views showing a method for manufacturing a semiconductor device of one embodiment of the present invention.

FIG. 18 A top view and cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 19 A top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.

FIG. 20 A cross-sectional view showing a structure of a memory device according to one embodiment of the present invention.

FIG. 21 A cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.

FIG. 22 A block diagram and a perspective view showing a configuration example of a memory device of one embodiment of the present invention.

FIG. 23 Circuit diagrams showing a configuration example of a memory device of one embodiment of the present invention.

FIG. 24 Schematic views of a semiconductor device of one embodiment of the present invention.

FIG. 25 Schematic views of memory devices of one embodiment of the present invention.

FIG. 26 Views each showing an electronic device according to one embodiment of the present invention.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to the drawings. Note that the embodiments can be implemented with many different modes, and it will be readily understood by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings schematically show ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which might not be reflected in the drawings for easy understanding. Furthermore, in the drawings, the same reference numerals are used in common for the same portions or portions having similar functions in different drawings, and repeated description thereof is omitted in some cases. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

In addition, particularly in a top view (also referred to as a plan view), a perspective view, or the like, the description of some components might be omitted for easy understanding of the invention. Furthermore, some hidden lines and the like might be omitted.

In addition, in this specification and the like, ordinal numbers such as “first” and “second” are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made by replacing “first” with “second,” “third,” or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which are used to specify one embodiment of the present invention in some cases.

In addition, in this specification and the like, terms for describing arrangement, such as “over” and “below,” are used for convenience to describe the positional relationship between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with a direction in which the components are described. Thus, terms for the description are not limited to those used in this specification, and description can be made appropriately depending on the situation.

When this specification and the like explicitly state that X and Y are connected, for example, the case whereXand Y are electrically connected, the case whereXand Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or text, a connection relationship other than a connection relationship shown in drawings or text is regarded as being disclosed in the drawings or the text.

Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can sometimes be interchanged with each other in this specification and the like.

Note that in this specification and the like, depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) is different from a channel width shown in a top view of a transistor (hereinafter also referred to as an “apparent channel width”) in some cases. For example, when a gate electrode covers a side surface of a semiconductor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor is increased in some cases. In that case, the effective channel width is greater than the apparent channel width.

In such a case, the effective channel width is sometimes difficult to estimate by actual measurement. For example, estimation of the effective channel width from a design value requires the assumption that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure the effective channel width accurately.

In this specification, the simple term “channel width” refers to an apparent channel width in some cases. Alternatively, in this specification, the simple term “channel width” refers to an effective channel width in some cases. Note that values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined, for example, by analyzing a cross-sectional TEM image and the like.

Note that impurities in a semiconductor refer to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, DOS (Density of States) in a semiconductor might be increased or crystallinity might be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given as examples. In the case of an oxide semiconductor, water also serves as an impurity in some cases. Also in the case of an oxide semiconductor, oxygen vacancies are formed by the entry of impurities, for example. Furthermore, when the semiconductor is silicon, examples of an impurity that changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

Note that in this specification and the like, silicon oxynitride is a material that contains more oxygen than nitrogen in its composition. Moreover, silicon nitride oxide is a material that contains more nitrogen than oxygen in its composition.

In addition, in this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Furthermore, the term “conductor” can be replaced with a conductive film or a conductive layer. Moreover, the term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer.

In addition, in this specification and the like, “parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −10° and less than or equal to 10°. Accordingly, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. Furthermore, “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 80° and less than or equal to 100°. Accordingly, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Moreover, “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°.

Note that in this specification, a barrier film means a film having a function of inhibiting the passage of oxygen and impurities such as water or hydrogen; in the case where the barrier film has conductivity, the barrier film is referred to as a conductive barrier film in some cases.

In this specification and the like, a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, in the case where an OS FET or an OS transistor is stated, the transistor can also be referred to as a transistor including an oxide or an oxide semiconductor.

In addition, in this specification and the like, “normally off” means that current per micrometer of a channel width flowing through a transistor when a potential is not applied to a gate or a ground potential is applied to the gate is lower than or equal to 1×10⁻²⁰ A at room temperature, lower than or equal to 1×10⁻¹⁸ A at 85° C., or lower than or equal to 1×10⁻¹⁶ A at 125° C.

Embodiment 1

A specific structure example of a semiconductor device including a transistor 200 of one embodiment of the present invention will be described with reference to FIG. 1 to FIG. 19.

<Structure Example of Semiconductor Device>

FIG. 1(A), FIG. 1(B), FIG. 1(C), and FIG. 1(D) are a top view and cross-sectional views of the transistor 200 of one embodiment of the present invention and the periphery of the transistor 200.

FIG. 1(A) is a top view of a semiconductor device including the transistor 200. FIG. 1(B) and FIG. 1(C) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 1(A), and is a cross-sectional view in the channel length direction of the transistor 200. In addition, FIG. 1(C) is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1(A), and is a cross-sectional view in the channel width direction of the transistor 200. FIG. 1(D) is a cross-sectional view of a portion indicated by dashed-dotted line A5-A6 in FIG. 1(A). Note that for clarity of the drawing, some components are not shown in the top view of FIG. 1(A). FIG. 2 is an enlarged view of an oxide 230 b and the vicinity thereof in FIG. 1(B).

[Transistor 200]

As shown in FIG. 1, the transistor 200 includes an oxide 230 a positioned over a substrate (not shown), the oxide 230 b positioned over the oxide 230 a, a layer 253 a and a layer 253 b separately formed from each other in the top surface of the oxide 230 b, a layer 252 a and a layer 252 b separately formed from each other between the layer 253 a and the layer 253 b, an insulator 280 which is positioned over the oxide 230 b and in which part of an opening 263 is formed to overlap the region between the layer 253 a and the layer 253 b, a conductor 260 positioned in the opening 263, an insulator 250 positioned between the oxide 230 b and the conductor 260 and between the insulator 280 and the conductor 260, and an oxide 230 c positioned between the oxide 230 b and the insulator 250 and between the insulator 280 and the insulator 250. Here, as shown in FIGS. 1(B) and 1(C), the top surface of the conductor 260 is preferably substantially aligned with the top surfaces of the insulator 250, the oxide 230 c, and the insulator 280.

Hereinafter, the oxide 230 a, the oxide 230 b, and the oxide 230 c may be collectively referred to as an oxide 230. The layer 252 a and the layer 252 b may be collectively referred to as a layer 252. The layer 253 a and the layer 253 b may be collectively referred to as a layer 253.

Furthermore, as shown in FIG. 1, an insulator 256 is preferably positioned between the insulator 280 and the insulator 224, the oxide 230 a, and the oxide 230 b. Here, as shown in FIGS. 1(B) and 1(C), the insulator 256 is preferably in contact with the top surface and the side surface of the layer 253 a, the top surface and the side surface of the layer 253 b, the side surface of the oxide 230 c, and the top surface of the insulator 224.

Furthermore, as shown in FIG. 1, an insulator 266 is preferably positioned between the insulator 256 and the insulator 280. Here, as shown in FIGS. 1(B) and 1(C), the insulator 266 is preferably in contact with the top surface of the insulator 256, the side surface of the oxide 230 c, to and the bottom surface of the insulator 280.

Note that although a structure of the transistor 200 in which three layers of the oxide 230 a, the oxide 230 b, and the oxide 230 c are stacked in a region where a channel is formed (hereinafter also referred to as a channel formation region) and its vicinity is shown, the present invention is not limited thereto. For example, a two-layer structure of the oxide 230 b and the oxide 230 c or a stacked-layer structure of four or more layers may be employed. Alternatively, each of the oxide 230 a, the oxide 230 b, and the oxide 230 c may have a stacked-layer structure of two or more layers. Although the conductor 260 is shown to have a stacked-layer structure of two layers in the transistor 200, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.

For example, when the oxide 230 c has a stacked-layer structure including a first oxide and a second oxide over the first oxide, the first oxide preferably has a composition similar to that of the oxide 230 b and the second oxide preferably has a composition similar to that of the oxide 230 a.

Here, the conductor 260 functions as a gate electrode of the transistor, and the layers 252 a and 253 a and the layers 252 b and 253 b function as a source region or a drain region. As described above, the conductor 260 is formed to be embedded in the opening 263 in the insulator 280, the insulator 266, and the insulator 256. The opening 263 is formed in a region interposed between the layer 253 a and the layer 253 b. Here, the positions of the conductor 260, the layer 252 a, the layer 252 b, the layer 253 a, and the layer 253 b are selected in a self-aligned manner with respect to the opening 263. That is, in the transistor 200, the gate electrode can be positioned between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 260 can be formed without an alignment margin, resulting in a reduction in area occupied by the transistor 200. Accordingly, miniaturization and high integration of the semiconductor device can be achieved.

In addition, as shown in FIG. 1, the conductor 260 preferably includes the conductor 260 a provided in the insulator 250 and the conductor 260 b embedded in the conductor 260 a.

The transistor 200 preferably further includes an insulator 214 positioned over the substrate (not shown); an insulator 216 positioned over the insulator 214; a conductor 205 positioned to be embedded in the insulator 216; an insulator 222 positioned over the insulator 216 and the conductor 205; and the insulator 224 positioned over the insulator 222. The oxide 230 a is preferably positioned over the insulator 224.

An insulator 274 and an insulator 281 functioning as interlayer films are preferably positioned over the transistor 200. Here, the insulator 274 is preferably positioned in contact with the top surfaces of the conductor 260, the insulator 250, the oxide 230 c, and the insulator 280.

It is preferable that the insulator 222, the insulator 256, the insulator 266, and the insulator 274 have a function of inhibiting diffusion of hydrogen (e.g., a hydrogen atom, a hydrogen molecule, and the like). For example, the insulator 222, the insulator 256, the insulator 266, and the insulator 274 preferably have a lower hydrogen permeability than the insulator 224, the insulator 250, and the insulator 280. It is also preferable that the insulator 222, the insulator 256, the insulator 266, and the insulator 274 have a function of inhibiting diffusion of oxygen (e.g., an oxygen atom, an oxygen molecule, and the like). For example, the insulator 222, the insulator 256, the insulator 266, and the insulator 274 preferably have a lower oxygen permeability than the insulator 224, the insulator 250, and the insulator 280.

Here, the insulator 224, the oxide 230 a, the oxide 230 b, and the insulator 250 are separated from the insulator 280 and the insulator 281 by the insulator 256, the insulator 266, the oxide 230 c, and the insulator 274. Thus, the entry of impurities such as hydrogen and excess oxygen contained in the insulator 280 and the insulator 281 into the insulator 224, the oxide 230 a, the oxide 230 b, and the insulator 250 can be inhibited.

In addition, as shown in FIGS. 1(B) and 1(D), a conductor 240 (a conductor 240 a and a conductor 240 b) that is electrically connected to the transistor 200 and functions as a plug is preferably provided. Note that an insulator 241 (an insulator 241 a and an insulator 241 b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In other words, the insulator 241 is provided in contact with the inner wall of the opening in the insulator 256, the insulator 266, the insulator 280, the insulator 274, and the insulator 281. Alternatively, a structure may be employed in which a first conductor of the conductor 240 is provided in contact with a side surface of the insulator 241 and a second conductor of the conductor 240 is provided on the inner side of the first conductor. Here, the top surface of the conductor 240 and the top surface of the insulator 281 can be substantially level with each other. Note that although the transistor 200 having a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or to have a stacked-layer structure of three or more layers. When a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.

In addition, in the transistor 200, as the oxide 230 (the oxide 230 a, the oxide 230 b, and the oxide 230 c) that includes the channel formation region, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, it is preferable to use a metal oxide having a bandgap more than or equal to 2 eV, preferably more than or equal to 2.5 eV as the metal oxide to be the channel formation region of the oxide 230. With use of a metal oxide having such a wide bandgap, the leakage current in a non-conduction state (off-state current) of the transistor can be extremely reduced. With use of such a transistor, a semiconductor device with low power consumption can be provided.

For example, as the oxide 230, a metal oxide such as an In-M-Zn oxide (the element M is one kind or a plurality of kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. In particular, aluminum, gallium, yttrium, or tin is preferably used for the element M. Furthermore, indium oxide, zinc oxide, an In—Ga oxide, an In-Zn oxide, a Ga-Zn oxide, or gallium oxide may be used as the oxide 230.

When an element that forms an oxygen vacancy or an element that is bonded to an oxygen vacancy is added to the oxide 230, the carrier density is increased and the resistance is lowered in some cases. Typical examples of the element include boron and phosphorus. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas, or the like can be used as well as boron and phosphorus. Typical examples of the rare gas include helium, neon, argon, krypton, and xenon. Furthermore, any one or more metal elements selected from metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum may be added to the oxide 230. Among the above-described elements, boron or phosphorus is preferable as the element to be added. Since an apparatus in a manufacturing line for amorphous silicon or low-temperature polysilicon can be used for the addition of boron or phosphorus, capital investment can be reduced. The concentration of the above element is measured by secondary ion mass spectrometry (SIMS) or the like.

In particular, an element that easily forms an oxide is preferably used as an element to be added to the oxide 230. Typical examples of the element include boron, phosphorus, aluminum, and magnesium. The element added to the oxide 230 can deprive oxygen in the oxide 230 to form an oxide. As a result, many oxygen vacancies are generated in the oxide 230. When the oxygen vacancies and hydrogen in the oxide 230 are bonded to each other, carriers are generated, and accordingly, a region with extremely low resistance is formed. The element added to the oxide 230 exists in the state of a stable oxide in the oxide 230; thus, even when treatment that requires a high temperature is performed in a later step, the element is not easily released from the oxide 230. That is, the use of an element that easily forms an oxide as an element to be added to the oxide 230 enables formation of a region whose resistance is not easily increased even through a high-temperature process in the oxide 230.

The layer 252 is formed through addition of the above element to the oxide 230. As shown in FIG. 1(B) and FIG. 2, the layer 252 a and the layer 252 b are formed to face each other with the conductor 260 therebetween, and the top surfaces are preferably in contact with the oxide 230 c. In the top view, it is preferable that at least part of the layer 252 a and part of the layer 252 b overlap with the conductor 260. Here, the concentration of the element in the layer 252 is preferably higher than that in the part of the oxide 230 where the layer 252 and the layer 253 are not formed. It is preferable that the amount of oxygen vacancies in the layer 252 be larger than the amount of oxygen vacancies in the part of the oxide 230 where the layer 252 and the layer 253 are not formed. Accordingly, the layer 252 has a higher carrier density and lower resistance than the part of the oxide 230 where the layer 252 and the layer 253 are not formed.

The layer 253 is a layer formed through addition of the above element to the oxide 230 and is formed to contain a larger amount of the element than the layer 252. As shown in FIG. 1(B) and FIG. 2, the layer 253 a and the layer 253 b are formed to face each other with the conductor 260 and the layer 252 positioned therebetween, and the top surfaces are preferably in contact with the insulator 256 and the oxide 230 c. In the top view, it is preferable that side surfaces of the layer 253 a and the layer 253 b on the conductor 260 side be aligned with a side surface of the conductor 260, or that part of the layer 253 a and part of the layer 253 b overlap with the conductor 260. Here, the concentration of the element in the layer 253 is preferably higher than or equal to that in the layer 252. Furthermore, the amount of oxygen vacancies in the layer 253 is preferably larger than that in the part of the oxide 230 where the layer 252 and the layer 253 are not formed. Accordingly, the layer 253 has a higher carrier density and lower resistance than the part of the oxide 230 where the layer 252 and the layer 253 are not formed.

As shown in FIG. 2, in the oxide 230, the region which overlaps with the conductor 260 and is interposed between the layer 252 a and the layer 252 b is denoted as a region 234, the region which overlaps with the layer 253 is a region 231 (a region 231 a and a region 231 b), and the region which overlaps with the layer 252 is a region 232 (a region 232 a and a region 232 b). As shown in FIG. 2, the region 234 is positioned between the region 231 a and the region 231 b, the region 232 a is positioned between the region 231 a and the region 234, and the region 232 b is positioned between the region 231 b and the region 234. The region 231 has a higher carrier density and lower resistance than the region 234. The region 232 has a higher carrier density and lower resistance than the region 234 and has a lower carrier density and higher resistance than the region 231. Alternatively, the region 232 may have an equivalent level of a carrier density and resistance to the region 231. Accordingly, the region 234 functions as a channel formation region of the transistor 200, the region 231 functions as a source region or a drain region, and the region 232 functions as a junction region.

With the above structure, the layer 252 overlapping with the conductor 260 functions as a so-called overlap region (also referred to as an Lov region). With the structure, an offset region is prevented from being formed between the channel formation region and the source region or the drain region in the oxide 230, so that an effective channel length can be inhibited from being longer than the width of the conductor 260. Accordingly, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics.

The formation of the region 231 functioning as the source region or the drain region in the oxide 230 enables the conductor 240 functioning as a plug to be connected to the region 231 without providing a source electrode and a drain electrode that are formed using a metal. When the source electrode and the drain electrode formed using a metal are provided in contact with the oxide 230, in the case where high-temperature heat treatment is performed in the manufacturing process of the transistor 200 or the subsequent process, the source electrode and the drain electrode formed with a metal might be oxidized, and the on-state current, the S-value, and the frequency characteristics of the transistor 200 are degraded in some cases. However, in the semiconductor device in this embodiment, it is not necessary to provide the source electrode and the drain electrode formed using metal. Thus, the transistor 200 can have a favorable on-state current, S-value, and frequency characteristics even when high-temperature heat treatment is performed in the manufacturing process of the transistor 200 or the subsequent process. For example, in the semiconductor device in this embodiment, a process in which a high temperature higher than or equal to 450° C. and lower than or equal to 800° C., typically higher than or equal to 600° C. and lower than or equal to 750° C. is applied can be performed after the transistor 200 is manufactured.

By adding an element that forms an oxygen vacancy to the layer 252 and the layer 253 and performing heat treatment as described above, hydrogen contained in the region 234 functioning as the channel formation region can be trapped by oxygen vacancies included in the layer 253, in some cases. Here, it is preferable that the concentration of hydrogen contained in the layer 253 or the layer 252 be higher than the concentration of hydrogen in the part of the oxide 230 where the layer 252 and the layer 253 are not formed. Thus, the transistor 200 can have stable electrical characteristics and increased reliability.

Furthermore, the transistor 200 is formed using the manufacturing method described in this embodiment, whereby the conductor 260 can be provided between the layer 253 a and the layer 253 b in a self-aligned manner and can overlap with the layer 252 a and the layer 252 b, which will be described in detail later. Thus, the semiconductor device with favorable electrical characteristics can be manufactured with a high yield. Furthermore, a channel length (which can also referred to as the length of the region 234 in the A1-A2 direction or the distance between the layers 252 a and 252 b) can be less than the resolution limit of the light exposure apparatus. For example, the channel length can be greater than or equal to 1 nm and less than or equal to 60 nm, preferably greater than or equal to 15 nm and less than or equal to 40 nm. By making the channel length short, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics.

As a manufacturing method of the semiconductor device, the layer 252 and the layer 253 are preferably formed through the addition of the above element as a dopant to the oxide 230 through the insulator 256, which will be described in detail later. Here, the dopant is added not only to the oxide 230 but also to the insulator 256 in some cases.

The dopant added to the region 231 and the region 232 in the oxide 230 is bonded to oxygen in the oxide 230; thus, in the region 231 and the region 232 in the oxide 230, oxygen vacancies are generated. Here, it can be considered that hydrogen contained in the region 234 in the oxide 230 is diffused into the region 231 and the region 232 and is captured by the oxygen vacancies, and thus the resistance of the oxide 230 in the region 234 is higher than that after the deposition. On the other hand, it can be considered that the resistance of the oxide 230 in the region 231 is lower than that after the deposition because the oxygen vacancies capture the hydrogen.

When the insulator 256 overlapping with the region 231 contains oxygen (or excess oxygen described later), the oxygen is diffused into the oxide 230, which might make the resistance of the oxide 230 in the region 231 high; thus, the region 231 may not sufficiently function as the source region and the drain region. However, the dopant is added to the insulator 256, whereby oxygen contained in the insulator 256 is trapped by the dopant and fixed. Thus, release of oxygen from the insulator 256 is suppressed, and the resistance of the oxide 230 in the region 231 can be kept lower than that after the deposition.

It can be considered that according to the above mechanism, in the oxide 230, the region 234 maintains high resistance and can function as a channel formation region, and the region 231 maintains low resistance and can function as a source region or a drain region. Since the dopant added to the oxide 230 is not diffused by heat treatment in the subsequent process and is stable, the region 234, the region 232, and the region 231 are stable without expansion or contraction even when the heat treatment is performed. In other words, the transistor in this invention has a reduced possibility of defects of electrical characteristics and reliability such as increase or decrease of the channel length or a connection between a source region and a drain region through heat treatment.

Note that although the layer 252 and the layer 253 are formed in the vicinity of the interface between the oxide 230 b and the insulator 256 and between the oxide 230 b and the oxide 230 c in the thickness direction of the oxide 230 b in FIG. 2, the present invention is not limited thereto. For example, the layer 252 and the layer 253 may have substantially the same thickness as the oxide 230 b or may also be formed in the oxide 230 a.

In the oxide 230, the boundaries between the regions are difficult to be detected clearly in some cases. The concentration of a metal element and an impurity element such as hydrogen and nitrogen, which is detected in each region, may be not only gradually changed between the regions, but also continuously changed (also referred to as gradation) in each region. That is, the region closer to the channel formation region has a lower concentration of a metal element and an impurity element such as hydrogen and nitrogen.

Note that although FIG. 2 shows a structure in which the conductor 260 overlaps the region 234 and the region 232 (the layer 252), this embodiment is not limited thereto. For example, as shown in FIG. 3, the conductor 260 may overlap with the region 234, the region 232 (the layer 252), and part of the region 231 (the layer 253). With this structure, in addition to the layer 252 overlapping with the conductor 260, part of the layer 253 functions as an overlap region. Thus, an offset region is prevented from being formed between the channel formation region and the source region or the drain region in the oxide 230 with more certainty, so that an effective channel length can be inhibited from being longer than the width of the conductor 260. Accordingly, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics.

Accordingly, a semiconductor device including a transistor with a high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high frequency characteristics can be provided. Alternatively, a semiconductor device that has stable electrical characteristics with reduced variations in electrical characteristics and higher reliability can be provided. Alternatively, a semiconductor device including a transistor with a low off-state current can be provided.

The detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention is described below.

The conductor 205 is positioned to overlap with the oxide 230 and the conductor 260.

Furthermore, the conductor 205 is preferably provided to be embedded in the insulator 216. Here, the top surface of the conductor 205 preferably has favorable planarity. For example, the average surface roughness (Ra) of the top surface of the conductor 205 is less than or equal to 1 nm, preferably less than or equal to 0.5 nm, further preferably less than or equal to 0.3 nm. This allows the improvement in favorable planarity of the insulator 224 formed over the conductor 205 and the increase in crystallinity of the oxide 230 a, the oxide 230 b and the oxide 230 c.

Here, the conductor 260 sometimes functions as a first gate (also referred to as top gate) electrode. Alternatively, the conductor 205 sometimes functions as a second gate (also referred to as bottom gate) electrode. In that case, V_(th) of the transistor 200 can be controlled by changing a potential applied to the conductor 205 independently of a potential applied to the conductor 260. In particular, V_(th) of the transistor 200 can be higher than 0 V and the off-state current can be reduced by applying a negative potential to the conductor 205. Thus, a drain current when a potential applied to the conductor 260 is 0 V can be lower in the case where a negative potential is applied to the conductor 205 than in the case where the negative potential is not applied to the conductor 205.

In addition, the conductor 205 is preferably provided larger than the channel formation region of the oxide 230. As shown in FIG. 1(C), it is particularly preferable that the conductor 205 also extend to a region outside an end portion of the oxide 230 that intersects with the channel width direction. That is, the conductor 205 and the conductor 260 preferably overlap with each other with the insulators therebetween on an outer side of the side surface of the oxide 230 in the channel width direction.

Since the above-described structure is included, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.

Furthermore, as shown in FIG. 1(C), the conductor 205 is extended to function as a wiring as well. However, without limitation to this structure, a structure where a conductor functioning as a wiring is provided below the conductor 205 may be employed. In addition, the conductor 205 is not necessarily provided in each transistor. For example, the conductor 205 may be shared by a plurality of transistors.

In the conductor 205, a first conductor is formed in contact with the inner wall of the opening in the insulator 216, and a second conductor is formed on the inner side. Here, the top surfaces of the first conductor of the conductor 205 and the second conductor thereof and the top surface of the insulator 216 can be substantially level with each other. Note that although the transistor 200 having a structure in which the first conductor of the conductor 205 and the second conductor thereof are stacked is shown, the present invention is not limited thereto. For example, the conductor 205 may have a single-layer structure or a stacked-layer structure of three or more layers. When a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.

In addition, a conductor having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N₂O, NO, NO₂, or the like), and a copper atom (a conductor through which the above impurities are less likely to pass) may be used for the first conductor of the conductor 205. Alternatively, it is preferable to use a conductor having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (through which oxygen is less likely to pass). Note that in this specification, a function of inhibiting diffusion of impurities or oxygen means a function of inhibiting diffusion of any one or all of the above impurities and oxygen.

When a conductor having a function of inhibiting oxygen diffusion is used for the first conductor of the conductor 205, the conductivity of the conductor 205 can be inhibited from being lowered because of oxidation. As the conductor having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Accordingly, the first conductor of the conductor 205 may be a single layer or stacked layers of the above conductive materials.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the second conductor of the conductor 205.

An insulator 214 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor 200 from the substrate side. Accordingly, for the insulator 214, it is preferable to use an insulating material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N₂O, NO, NO₂, or the like), and a copper atom (an insulating material through which the above impurities are less likely to pass).

Alternatively, it is preferable to use an insulating material that has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (through which the above oxygen is less likely to pass).

For example, aluminum oxide, silicon nitride, or the like is preferably used for the insulator 214. Accordingly, impurities such as water or hydrogen can be inhibited from being diffused into the transistor 200 side from the substrate side through the insulator 214. Alternatively, oxygen contained in the insulator 224 and the like can be inhibited from being diffused into the substrate side through the insulator 214.

In addition, the permittivity of the insulator 216, the insulator 280, and the insulator 281 each functioning as an interlayer film is preferably lower than that of the insulator 214. When a material with a low permittivity is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced. For each of the insulator 216, the insulator 280, and the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate, for example.

The insulator 216 may have a stacked-layer structure. For example, the insulator 216 may include an insulator similar to the insulator 214 at least in the region that is in contact with a side surface of the conductor 205. Owing to this structure, oxidation of the conductor 205 by the oxygen contained in the insulator 216 can be inhibited. Alternatively, owing to the conductor 205, absorption of oxygen contained in the insulator 216 can be suppressed.

The insulator 222 and the insulator 224 each have a function of a gate insulator.

Here, it is preferable that oxygen be released from the insulator 224 in contact with the oxide 230 by heating. In this specification, oxygen that is released by heating is referred to as excess oxygen in some cases. For example, for the insulator 224, silicon oxide, silicon oxynitride, or the like is used as appropriate. When an insulator containing oxygen is provided in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

As the insulator 224, specifically, an oxide material from which part of oxygen is released by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is larger than or equal to 1.0×10¹⁸ atoms/cm³, preferably greater than or equal to 1.0×10¹⁹ atoms/cm³, further preferably greater than or equal to 2.0×10¹⁹ atoms/cm³ or greater than or equal to 3.0×10²⁰ atoms/cm³ in TDS (Thermal Desorption Spectroscopy) analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C.

In addition, as shown in FIG. 1(C), the region of the insulator 224 that does not overlap with the oxide 230 b preferably has smaller thickness than the other region of the insulator 224. With such a structure, the lower end portion of the conductor 260 can be positioned lower, and thus, the electric field of the conductor 260 functioning as the first gate electrode is easily applied to the side surface of the oxide 230. Thus, the on-state current of the transistor 200 can be increased and the frequency characteristics of the transistor 200 can be improved. Alternatively, the insulator 224 may have an island shape to overlap the oxide 230 b and the oxide 230 a.

Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor 200 from the substrate side. For example, the insulator 222 preferably has a lower hydrogen permeability than the insulator 224. When the insulator 224, the oxide 230, the insulator 250, and the like are surrounded by the insulator 222, the insulator 256, the insulator 266, and the insulator 274, impurities such as water or hydrogen can be inhibited from entering the transistor 200 from the outside.

It is preferable that the insulator 222 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (through which oxygen is less likely to pass). For example, the insulator 222 preferably has a lower oxygen permeability than the insulator 224. When the insulator 222 has a function of inhibiting diffusion of oxygen or impurities, oxygen contained in the oxide 230 can be inhibited from being diffused into the substrate side, which is preferable. Furthermore, the conductor 205 can be inhibited from reacting with oxygen contained in the insulator 224 or the oxide 230.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator 222 is formed using such a material, the insulator 222 functions as a layer that inhibits the release of oxygen from the oxide 230 and the entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

Alternatively, one selected from aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators, for example. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

Alternatively, for example, a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO₃), or (Ba,Sr)TiO₃ (BST) may be used for the insulator 222. With miniaturization and high integration of transistors, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept.

Note that the insulator 222 and the insulator 224 may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

The oxide 230 includes the oxide 230 a, the oxide 230 b over the oxide 230 a, and the oxide 230 c over the oxide 230 b. Including the oxide 230 a below the oxide 230 b makes it possible to inhibit diffusion of impurities into the oxide 230 b from the components formed below the oxide 230 a. Moreover, including the oxide 230 c over the oxide 230 b makes it possible to inhibit diffusion of impurities into the oxide 230 b from the components formed above the oxide 230 c.

Note that the oxide 230 preferably has a stacked-layer structure of oxides that differ in the atomic ratio of metal atoms. Specifically, the atomic ratio of the elementMto the constituent elements in the metal oxide used for the oxide 230 a is preferably greater than the atomic ratio of the element Mto the constituent elements in the metal oxide used for the oxide 230 b. Moreover, the atomic ratio of the element M to In in the metal oxide used for the oxide 230 a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230 b. Furthermore, the atomic ratio of In to the elementMin the metal oxide used for the oxide 230 b is preferably greater than the atomic ratio of In to the elementMin the metal oxide used for the oxide 230 a. A metal oxide that can be used for the oxide 230 a or the oxide 230 b can be used for the oxide 230 c.

The oxide 230 a, the oxide 230 b, and the oxide 230 c preferably have crystallinity, and in particular, a CAAC-OS is preferably used. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (oxygen vacancies or the like) and high crystallinity. The transistor 200 including the oxide 230 is stable with respect to a high temperature (so-called thermal budget) in a manufacturing process.

The energy of the conduction band minimum of each of the oxide 230 a and the oxide 230 c is preferably higher than the energy of the conduction band minimum of the oxide 230 b. In other words, the electron affinity of each of the oxide 230 a and the oxide 230 c is preferably smaller than the electron affinity of the oxide 230 b. In that case, a metal oxide that can be used for the oxide 230 a is preferably used for the oxide 230 c. Specifically, the atomic ratio of the elementM to the constituent elements in the metal oxide used for the oxide 230 c is preferably greater than the atomic ratio of the element Mto the constituent elements in the metal oxide used for the oxide 230 b. Moreover, the atomic ratio of the element M to In in the metal oxide used for the oxide 230 c is preferably greater than the atomic ratio of the element Mto In in the metal oxide used for the oxide 230 b. Furthermore, the atomic ratio of In to the element M in the metal oxide used for the oxide 230 b is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230 c.

The energy level of the conduction band minimum gradually changes at junction portions of the oxide 230 a, the oxide 230 b, and the oxide 230 c. In other words, the energy level of the conduction band minimum at the junction portions of the oxide 230 a, the oxide 230 b, and the oxide 230 c continuously changes or is continuously connected. To obtain this, the density of defect states in a mixed layer formed at an interface between the oxide 230 a and the oxide 230 b and an interface between the oxide 230 b and the oxide 230 c is preferably made low.

Specifically, when the oxide 230 a and the oxide 230 b or the oxide 230 b and the oxide 230 c contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide 230 b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used for the oxide 230 a and the oxide 230 c. The oxide 230 c may have a stacked-layer structure. For example, it is possible to employ a stacked-layer structure of an In—Ga—Zn oxide and a Ga—Zn oxide over the In—Ga—Zn oxide, or a stacked-layer structure of an In—Ga—Zn oxide and gallium oxide over the In—Ga—Zn oxide. In other words, a stacked-layer structure of an In—Ga—Zn oxide and an oxide that does not contain In may be used for the oxide 230 c.

Specifically, as the oxide 230 a, a metal oxide having In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] is used. As the oxide 230 b, a metal oxide having In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] is used. As the oxide 230 c, a metal oxide having In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] is used. Specific examples of the oxide 230 c having a stacked-layer structure include a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], a stacked-layer structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide, and the like.

At this time, the oxide 230 b and the vicinity of the interface serve as a main carrier path. When the oxide 230 a and the oxide 230 c have the above structure, the density of defect states at the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor 200 can have a high on-state current and high frequency characteristics. Note that in the case where the oxide 230 c has a stacked-layer structure, in addition to the reduction of density of defect states at the interface between the oxide 230 b and the oxide 230 c, the inhibition of diffusion of the constituent element of the oxide 230 c to the insulator 250 side is expected. More specifically, since the oxide 230 c has a stacked-layer structure in which an oxide that does not contain In is positioned in the upper layer, the diffusion of In into the insulator 250 side can be inhibited. Since the insulator 250 functions as a gate insulator, the transistor exhibits poor characteristics when In diffuses into the insulator 250. Thus, when the oxide 230 c has a stacked-layer structure, a highly reliable semiconductor device can be provided.

The insulator 250 functions as a gate insulator. The insulator 250 is preferably positioned in contact with the top surface of the oxide 230 c. For the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable.

As in the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably lowered. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits diffusion of oxygen from the insulator 250 to the conductor 260. Accordingly, the oxidation of the conductor 260 due to oxygen from the insulator 250 can be inhibited. For example, the metal oxide that can be used as the oxide 230 c is preferably used.

In addition, the metal oxide has a function of part of the gate insulator in some cases. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal to oxide that is a high-k material with high relative permittivity is preferably used for the metal oxide. When the gate insulator has a stacked-layer structure of the insulator 250 and the metal oxide, the stacked-layer structure can be thermally stable and have a high relative permittivity. Thus, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

Specifically, a metal oxide containing one kind or a plurality of kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

Although FIG. 1 shows the conductor 260 having a two-layer structure, the conductor 260 may have a single-layer structure or a stacked-layer structure of three or more layers.

For the conductor 260 a, it is preferable to use the above conductor having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N₂O, NO, NO₂, and the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

In addition, when the conductor 260 a has a function of inhibiting oxygen diffusion, the conductivity of the conductor 260 b can be inhibited from being lowered because of oxidation due to oxygen contained in the insulator 250. As a conductive material having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.

The conductor 260 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor 260 also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor 260 b may have a stacked-layer structure, for example, a stacked-layer structure of any of the above conductive materials and titanium or titanium nitride.

A metal oxide that can be used for the oxide 230 may be provided between the insulator 250 and the conductor 260 a. At this time, the metal oxide functions as a gate electrode like the conductor 260. The metal oxide is preferably provided because oxygen can be supplied to at least one of the insulator 250 and the oxide 230. Furthermore, when a metal oxide having a function of inhibiting the passage of oxygen is used as the metal oxide, the conductor 260 can be prevented from being oxidized by oxygen contained in the insulator 250 or the insulator 280. Alternatively, oxygen contained in the insulator 250 can be prevented from being absorbed by the conductor 260.

As shown in FIGS. 1(A) and 1(C), the side surface of the oxide 230 is positioned to be covered by the conductor 260 in a region of the oxide 230 b that does not overlap with the layer 252 and the layer 253, that is, in the channel formation region of the oxide 230. Accordingly, the electric field of the conductor 260 functioning as the first gate electrode is likely to act on the side surface of the oxide 230. Accordingly, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics.

Like the insulator 214 and the like, the insulator 256 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor 200 from the insulator 280 side. For example, the insulator 256 preferably has a lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 1(B) and 1(C), the insulator 256 is preferably in contact with part of the side surfaces of the oxide 230 c, the top surface and side surface of the layer 253 a, the top surface and side surface of the layer 253 b, that is, part of the top surface and side surfaces of the oxide 230 b, part of the side surfaces of the oxide 230 a, and the top surface of the insulator 224. Such a structure can inhibit the entry of hydrogen contained in the insulator 280 into the oxide 230 a, the oxide 230 b, and the insulator 224.

It is also preferable that the insulator 256 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (through which oxygen is less likely to pass). For example, the insulator 256 preferably has a lower oxygen permeability than the insulator 280 or the insulator 224.

Alternatively, the insulator 256 may be deposited by a sputtering method. When the insulator 256 is deposited by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of a region of the insulator 224 that is in contact with the insulator 256. Accordingly, oxygen can be supplied from the region to the oxide 230 through the insulator 224. Here, with the insulator 256 having a function of inhibiting upward oxygen diffusion, oxygen can be prevented from diffusing from the oxide 230 into the insulator 280. Moreover, with the insulator 222 having a function of inhibiting downward oxygen diffusion, oxygen can be prevented from diffusing from the oxide 230 into the substrate side. In this manner, oxygen is supplied to the channel formation region of the oxide 230. Accordingly, oxygen vacancies in the oxide 230 can be reduced, so that the transistor can be inhibited from becoming normally-on.

An insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited as the insulator 256, for example. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

The insulator 256 may have a stacked-layer structure. In the case where the insulator 256 has a stacked-layer structure, a second insulator may be formed by an ALD method over a first insulator which is formed by a sputtering method. At this time, the first insulator and the second insulator may be formed using the same material or different materials selected from the above materials. For example, the first insulator may be aluminum oxide formed by a sputtering method and the second insulator may be aluminum oxide formed by an ALD method. The film formed by an ALD method has high coverage and can be formed with high evenness over a step portion due to a component such as the oxide 230. In addition, a deposition defect of the first insulator formed by a spattering method can be compensated for, which is preferable.

An insulator containing aluminum nitride may be used as the insulator 256, for example. It is preferable to use a nitride insulator that satisfies the composition formula AlN, (x is a real number greater than 0 and less than or equal to 2, preferably x is a real number greater than 0.5 and less than or equal to 1.5) as the insulator 256. Accordingly, a film having an excellent insulating property and high thermal conductivity can be obtained, and thus the dissipation of heat generated in driving the transistor 200 can be increased. Alternatively, aluminum titanium nitride, titanium nitride, or the like can be used for the insulator 256. In that case, deposition of the insulator 256 by a sputtering method is preferable because deposition can be performed without using a highly oxidizing gas such as oxygen or ozone as a deposition gas. Alternatively, silicon nitride, silicon nitride oxide, or the like can be used.

As described above, the insulator 224 and the oxide 230 are covered by the insulator 256 having a barrier property against hydrogen, whereby the insulator 280 is separated from the insulator 224 and the metal oxide 230. This can inhibit the entry of impurities such as hydrogen from the outside of the transistor 200, resulting in favorable electrical characteristics and high reliability of the transistor 200.

An insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited as the insulator 256, for example. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In this case, the insulator 256 is preferably deposited by an ALD method. An ALD method is a deposition method achieving excellent step coverage, and thus can prevent formation of disconnection or the like due to unevenness of the deposited surface.

The insulator 256 may function as a protective film when the layers 252 and 253 are formed, which will be described later. In the case where ion implantation or ion doping is used for formation of the layer 252 and the layer 253, it is preferable that the insulator 256 be formed as a protective film, so that a surface of the oxide 230 is not directly exposed to ions and plasma to reduce damage on the oxide 230 in the formation of the layer 252 and the layer 253. Here, the damage on the oxide 230 means, for example, formation of an excessive amount of oxygen vacancies in the oxide 230 and excessive decline of crystallinity of the oxide 230. For the insulator 256, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like can be used, for example. As the insulator 256, the barrier insulating film may further be stacked over the insulator functioning as a protective film.

Like the insulator 214 and the like, the insulator 266 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the transistor 200 from the insulator 280 side. For example, the insulator 266 preferably has a lower hydrogen permeability than the insulator 224. In addition, the insulator 266 is preferably positioned to be in contact with the top surface of the insulator 256 and the side surfaces of the oxide 230 c as shown in FIGS. 1(B) and 1(C). Such a structure can inhibit the entry of hydrogen contained in the insulator 280 into the oxide 230 and the insulator 224.

Thus, the insulator 224, the insulator 250, and the oxide 230 are covered by the insulator 256 and the insulator 266 having a barrier property against hydrogen, whereby the insulator 280 is separated from the insulator 224, the oxide 230, and the insulator 250. This can inhibit the entry of impurities such as hydrogen from the outside of the transistor 200, offering favorable electrical characteristics and high reliability to the transistor 200.

In addition, it is preferable that the insulator 266 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (through which oxygen is less likely to pass). For example, the insulator 266 preferably has a lower oxygen permeability than the insulator 224. When the insulator 266 has a function of inhibiting oxygen diffusion, the conductor 260 can be inhibited from reacting with oxygen contained in the insulator 280.

As the insulator 266, for example, a barrier insulating film that can be used for the insulator 256 can be used. Note that when the insulator 256 has a sufficient barrier property against hydrogen, the insulator 266 is not necessarily formed using a barrier insulating film.

The insulator 280 is provided over the insulator 224 and the oxide 230 with the insulator 256 and the insulator 266 therebetween. For example, for the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is preferably included. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide, in each of which a region containing oxygen released by heating can be easily formed, are particularly preferable.

The concentration of impurities such as water or hydrogen in the insulator 280 is preferably lowered. In addition, the top surface of the insulator 280 may be planarized.

Like the insulator 214 and the like, the insulator 274 preferably functions as a barrier insulating film that inhibits the entry of impurities such as water or hydrogen into the insulator 280 from the above. For example, the insulator 274 preferably has a lower hydrogen permeability than the insulator 280.

In addition, it is preferable that the insulator 274 have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (that oxygen is less likely to pass). For example, the insulator 274 preferably has a lower oxygen permeability than the insulator 280. When the insulator 274 has a function of inhibiting diffusion of oxygen, diffusion of oxygen contained in the insulator 280 to the outside can be inhibited.

As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 222, or the like is used. Furthermore, a barrier insulating film against impurities such as water or hydrogen and an insulating film having a function of inhibiting diffusion of oxygen may be stacked.

An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. As in the insulator 224 or the like, the concentration of impurities such as water or hydrogen in the insulator 281 is preferably lowered.

In addition, the conductor 240 a and the conductor 240 b are positioned in the openings formed in the insulator 281, the insulator 274, the insulator 280, the insulator 266, and the insulator 256. The conductor 240 a and the conductor 240 b are provided to face each other with the conductor 260 therebetween. Note that the level of the top surfaces of the conductor 240 a and the conductor 240 b may be on the same surface as the top surface of the insulator 281.

Note that the insulator 241 a is provided in contact with the inner wall of the opening in the insulator 281, the insulator 274, the insulator 280, the insulator 266, and the insulator 256, and the first conductor of the conductor 240 a is formed in contact with a side surface of the insulator 241 a. The layer 253 a is located on at least part of the bottom portion of the opening, and thus the conductor 240 a is in contact with the layer 253 a. Here, as shown in FIG. 1(D), the first conductor of the conductor 240 a is preferably in contact with the top surface and the side surface of the layer 253 a (also referred to as the top surface and the side surfaces of the oxide 230 b). When the conductor 240 a is provided in this manner, the contact area between the conductor 240 a and the layer 253 a increases, so that the on-state current and the mobility of the transistor 200 can be improved and the S-value of the transistor 200 can be reduced. Similarly, the insulator 241 b is provided in contact with the inner wall of the opening in the insulator 281, the insulator 274, the insulator 280, the insulator 266, and the insulator 256, and the first conductor of the conductor 240 b is formed in contact with a side surface of the insulator 241 b. The layer 253 b is located on at least part of the bottom portion of the opening, and thus the conductor 240 b is in contact with the layer 253 b. Although not shown, the first conductor of the conductor 240 b is preferably in contact with the top surface and the side surface of the layer 253 b (also referred to as the top surface and the side surfaces of the oxide 230 b), as in the case of the conductor 240 a. When the conductor 240 b is provided in this manner, the contact area between the conductor 240 b and the layer 253 b increases, so that the on-state current and the mobility of the transistor 200 can be improved and the S-value of the transistor 200 can be reduced.

For the conductor 240 a and the conductor 240 b, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. In addition, the conductor 240 a and the conductor 240 b may have a stacked-layer structure.

In addition, in the case where the conductor 240 has a stacked-layer structure, the conductor having a function of inhibiting diffusion of impurities such as water or hydrogen is preferably used as a conductor in contact with the oxide 230 a, the oxide 230 b, the insulator 256, the insulator 266, the insulator 280, the insulator 274, and the insulator 281. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Alternatively, the conductive material having a function of inhibiting diffusion of impurities such as water or hydrogen may be used as a single layer or stacked layers. The use of the conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductor 240 a and the conductor 240 b. Moreover, impurities such as water or hydrogen can be inhibited from entering the oxide 230 through the conductor 240 a and the conductor 240 b from a layer above the insulator 281 can be inhibited.

For the insulator 241 a and the insulator 241 b, an insulator that can be used for the insulator 214 or the like, for example, aluminum oxide or silicon nitride can be used. Since the insulator 241 a and the insulator 241 b are provided in contact with the insulator 256 and the insulator 266, the entry of impurities such as water or hydrogen into the oxide 230 through the conductor 240 a and the conductor 240 b from the insulator 280 or the like can be inhibited. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240 a and the conductor 240 b.

An ALD method or a CVD method can be used for formation of the insulator 241 a and the insulator 241 b.

In addition, although not shown, a conductor functioning as a wiring may be provided in contact with the top surface of the conductor 240 a and the top surface of the conductor 240 b. For the conductor functioning as a wiring, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. Furthermore, the conductor may have a stacked-layer structure; for example, stacked layers of the above conductive material, and titanium or titanium nitride. The conductor may be formed to be embedded in the openings provided in an insulator.

In addition, although not shown, an insulator having a resistivity higher than or equal to 1.0×10¹³ Ωcm and lower than or equal to 1.0×10¹⁵ Ωcm, preferably higher than or equal to 5.0×10¹³ Ωcm and lower than or equal to 5.0×10¹⁴ Ωcm is preferably provided to cover the conductor. It is preferable that an insulator having a resistivity in the above range be provided over the conductor, in which case the insulator can disperse electric charge accumulated between the transistor 200 and the wiring such as the conductor, and can inhibit poor characteristics and electrostatic breakdown of the transistor and an electronic device including the transistor due to the electric charge, while maintaining the insulating property.

FIG. 4 shows the transistor 200 including the oxide 230 c, the insulator 256, and the insulator 274 for each of which a stacked insulating film is used. Like in FIG. 1, FIGS. 4(A) to 4(D) are a top view and cross-sectional views of the transistor 200 and the periphery of the transistor 200. FIG. 4(A) is a top view of a semiconductor device including the transistor 200. FIG. 4(B) and FIG. 4(C) are cross-sectional views of the semiconductor device. Here, FIG. 4(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 4(A), and is a cross-sectional view in the channel length direction of the transistor 200. FIG. 4(C) is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 4(A), and is a cross-sectional view in the channel width direction of the transistor 200. FIG. 4(D) is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 4(A). Note that for simplification of the drawing, some components are not shown in the top view in FIG. 4(A).

In the transistor 200 shown in FIG. 4, an oxide 230 c 1 and an oxide 230 c 2 stacked thereover are used for the oxide 230 c, an insulator 256 a and an insulator 256 b stacked thereover are used for the insulator 256, and an insulator 274 a and an insulator 274 b stacked thereover are used for the insulator 274.

The metal oxide that can be used for the oxide 230 b is used for the oxide 230 c 1, and the metal oxide that can be used for the oxide 230 a is used for the oxide 230 c 2. For example, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] is used for the oxide 230 c 1 and a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] is used for the oxide 230 c 2.

As the insulator 256 a, an insulator is used that serves as a protective film in forming the layer 252 and the layer 253 and as the insulator 256 b, an insulator is used that serves as a barrier insulating film which inhibits the entry of impurities such as water or hydrogen. For the insulator 256 a, silicon oxide or silicon oxynitride can be used, for example. For the insulator 256 b, silicon nitride, silicon nitride oxide, aluminum nitride, or the like can be used.

As the insulator 274 a, an insulator is used that has a function of inhibiting diffusion of oxygen and as the insulator 274 b, an insulator is used that serves as a barrier insulating film which inhibits the entry of impurities such as water or hydrogen. For example, aluminum oxide formed by a sputtering method can be used for the insulator 274 a. The insulator 274 b can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, or the like.

<Constituent Material of Semiconductor Device>

Constituent materials that can be used for a semiconductor device are described below.

<<Substrate>>

As a substrate over which the transistor 200 is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate is used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (an yttria-stabilized zirconia substrate or the like), and a resin substrate. In addition, examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like and a compound semiconductor substrate containing silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate in which an insulator region is included in the semiconductor substrate, e.g., an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate including a metal nitride and a substrate including a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided for the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

<<Insulator>>

Examples of an insulator include an oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide, each of which has an insulating property.

As miniaturization and high integration of the transistor progress, for example, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, the voltage when the transistor operates can be reduced while keeping the physical thickness of the gate insulator. In contrast, when a material with a low relative permittivity is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

In addition, examples of the insulator with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

In addition, examples of the insulator with low a relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

When a transistor using an oxide semiconductor is surrounded by insulators having a function of inhibiting transmission of oxygen and impurities such as water or hydrogen (e.g., the insulator 214, the insulator 222, the insulator 256, the insulator 274, and the like), the electrical characteristics of the transistor can be stable. For the insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Specifically, as the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide or silicon nitride; or the like can be used.

In addition, the insulator functioning as the gate insulator is preferably an insulator including a region containing oxygen released by heating. For example, when a structure is employed in which silicon oxide or silicon oxynitride including a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies included in the oxide 230 can be compensated for.

<<Conductor>>

For the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing the above metal element; an alloy containing a combination of the above metal elements; or the like. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

A stack including a plurality of conductive layers formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. A stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. A stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

Note that when an oxide is used for the channel formation region of the transistor, a stacked-layer structure in which a material containing the above metal element and a conductive material containing oxygen are combined is preferably used for the conductor functioning as the gate electrode. In that case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen left from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide where the channel is formed. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. With use of such a material, hydrogen contained in the metal oxide where the channel is formed can be trapped in some cases. Alternatively, hydrogen entering from an external insulator or the like can be trapped in some cases.

<<Metal Oxide>>

As the oxide 230, a metal oxide functioning as an oxide semiconductor is preferably used. A metal oxide that can be applied to the oxide 230 according to the present invention is described below.

The oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. Furthermore, aluminum, gallium, yttrium, tin, or the like is preferably contained in addition to them. Furthermore, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

Here, the case where the oxide semiconductor is an In-M-Zn oxide that contains indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be applied to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. Note that it is sometimes acceptable to use a plurality of the above-described elements in combination as the element M.

Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride.

Oxide semiconductors are classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. A polycrystalline oxide semiconductor, an amorphous oxide semiconductor, and the like are known as non-single-crystal oxide semiconductors, for example.

For an oxide semiconductor used for a semiconductor of the transistor, a thin film having high crystallinity is preferably used. With use of the thin film, the stability or reliability of the transistor can be improved. Examples of the thin film include a thin film of a single crystal oxide semiconductor and a thin film of a polycrystalline oxide semiconductor. However, to form the thin film of a single crystal oxide semiconductor or the thin film of a polycrystalline oxide semiconductor over a substrate, a high-temperature process or a laser heating process is needed. Thus, manufacturing cost is increased, and throughput is decreased.

Non-Patent Document 1 and Non-Patent Document 2 have reported that an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was found in 2009. Here, it has been reported that CAAC-IGZO has c-axis alignment, a crystal grain boundary is not clearly observed in CAAC-IGZO, and CAAC-IGZO can be formed over a substrate at low temperatures. It has also been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and high reliability.

In addition, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was found in 2013 (see Non-Patent Document 3). Here, it has been reported that nc-IGZO has periodic atomic arrangement in a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) and there is no regularity of crystal orientation between different regions.

Non-Patent Document 4 and Non-Patent Document 5 have shown changes in average crystal size due to electron beam irradiation to thin films of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity. In the thin film of IGZO having low crystallinity, crystalline IGZO with a size of approximately 1 nm was observed even before electron beam irradiation. Thus, here, it has been reported that the existence of a completely amorphous structure could not be observed in IGZO. In addition, it has been shown that the thin film of CAAC-IGZO and the thin film of nc-IGZO each have higher stability to electron beam irradiation than the thin film of IGZO having low crystallinity. Thus, the thin film of CAAC-IGZO or the thin film of nc-IGZO is preferably used for the semiconductor of the transistor.

Non-Patent Document 6 has shown that a transistor using an oxide semiconductor has extremely low leakage current in a non-conduction state; specifically, an off-state current per micrometer of the channel width of the transistor is on the order of yA/μm (10⁻²⁴ A/μm). For example, a low-power-consumption CPU utilizing the property of low leakage current of the transistor using an oxide semiconductor has been disclosed (see Non-Patent Document 7).

Furthermore, application of a transistor using an oxide semiconductor to a display device utilizing the property of a low leakage current of the transistor has been reported (see Non-Patent Document 8). In the display device, a displayed image is changed several tens of times per second. The number of times an image is changed per second is referred to as a refresh rate. The refresh rate is also referred to as drive frequency. Such high-speed screen change that is hard for human eyes to recognize is considered as a cause of eyestrain. Thus, it is proposed that the refresh rate of the display device is lowered to reduce the number of times of image rewriting. Moreover, driving with a lowered refresh rate can reduce the power consumption of the display device. Such a driving method is referred to as idling stop (IDS) driving.

The finding of the CAAC structure and the nc structure has contributed to improvements in electrical characteristics and reliability of a transistor using an oxide semiconductor having the CAAC structure or the nc structure, a reduction in manufacturing cost, and an improvement in throughput. Furthermore, applications of the transistor to a display device and an LSI utilizing the property of a low leakage current of the transistor have been studied.

<Composition of Metal Oxide>

The composition of a CAC (Cloud-Aligned Composite)-OS that can be used in a transistor disclosed in one embodiment of the present invention will be described below.

Note that in this specification and the like, “c-axis aligned crystal (CAAC)” or “cloud-aligned composite (CAC)” might be stated. Note that CAAC refers to an example of a crystal structure, and CAC refers to an example of a function or a material composition.

A CAC-OS or a CAC-metal oxide has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS or the CAC-metal oxide has a function of a semiconductor. Note that in the case where the CAC-OS or the CAC-metal oxide is used in an active layer of a transistor, the conducting function is a function that allows electrons (or holes) serving as carriers to flow, and the insulating function is a function that does not allow electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, a switching function (On/Off function) can be given to the CAC-OS or the CAC-metal oxide. In the CAC-OS or the CAC-metal oxide, separation of the functions can maximize each function.

Furthermore, the CAC-OS or the CAC-metal oxide includes conductive regions and insulating regions. The conductive regions have the above-described conducting function, and the insulating regions have the above-described insulating function. Furthermore, in some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. Furthermore, in some cases, the conductive regions and the insulating regions are unevenly distributed in the material. Furthermore, the conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred, in some cases.

Furthermore, in the CAC-OS or the CAC-metal oxide, the conductive regions and the insulating regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm, and are dispersed in the material, in some cases.

Furthermore, the CAC-OS or the CAC-metal oxide includes components having different bandgaps. For example, the CAC-OS or the CAC-metal oxide includes a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of the structure, when carriers flow, carriers mainly flow in the component having a narrow gap. Furthermore, the component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, high current driving capability in an on state of the transistor, that is, a high on-state current and high field-effect mobility can be obtained.

In other words, the CAC-OS or the CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of Metal Oxide>

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

The CAAC-OS has c-axis alignment, a plurality of nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement in a region where the plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. Furthermore, a pentagonal or heptagonal lattice arrangement, for example, is included in the distortion in some cases. Note that a clear crystal grain boundary (also referred to as grain boundary) cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to the low density of oxygen atom arrangement in the a-b plane direction, a change in interatomic bond distance by replacement of a metal element, and the like.

Furthermore, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element Min the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. Furthermore, when indium in the In layer is replaced with the element M, the layer can be referred to as an (In,M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. Meanwhile, in the CAAC-OS, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur because a clear crystal grain boundary cannot be observed. Furthermore, the entry of impurities, formation of defects, or the like might decrease the crystallinity of the oxide semiconductor; thus, it can also be said that the CAAC-OS is an oxide semiconductor having small amounts of impurities and defects (oxygen vacancies or the like). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor that has a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS includes a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

An oxide semiconductor has various structures with different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

<Transistor Including Oxide Semiconductor>

Next, the case where the above oxide semiconductor is used for a transistor is described.

Note that when the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved.

In addition, an oxide semiconductor with a low carrier density is preferably used for a transistor. In the case where the carrier density of an oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film is lowered to decrease the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. For example, the carrier density of the oxide semiconductor is set lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and greater than or equal to 1×10⁻⁹/cm³.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.

Furthermore, electric charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and might behave like fixed electric charge. Thus, a transistor whose channel formation region is formed in an oxide semiconductor with a high density of trap states has unstable electrical characteristics in some cases.

Thus, in order to stabilize electrical characteristics of the transistor, reducing the impurity concentration in the oxide semiconductor is effective. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

[Impurity]

Here, the influence of each impurity in the oxide semiconductor is described.

When silicon or carbon, which is one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of an interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are each set lower than or equal to 2×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁷ atoms/cm³.

Furthermore, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Accordingly, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor that is obtained by SIMS is set lower than or equal to 1×10¹⁸ atoms/cm³, preferably lower than or equal to 2×10¹⁶ atoms/cm³.

Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. As a result, a transistor using an oxide semiconductor containing nitrogen in a semiconductor layer is likely to be normally-on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration in the oxide semiconductor that is obtained by SIMS is set, for example, lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³, still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. The entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor that is obtained by SIMS is set lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³, further preferably lower than 5×10¹⁸ atoms/cm³, still further preferably lower than 1×10¹⁸ atoms/cm³.

When an oxide semiconductor with sufficiently reduced impurities is used for the channel formation region of the transistor, stable electrical characteristics can be given.

[Effect of Vacuum Baking]

Here, a weak Zn—O bond included in a metal oxide is described, and an example of a method for reducing the number of oxygen atoms and zinc atoms that form the bond is described.

In a transistor using a metal oxide, an oxygen vacancy is given as an example of a defect that leads to poor electrical characteristics of the transistor. For example, the threshold voltage of a transistor using a metal oxide including oxygen vacancies in the film tends to shift in the negative direction, and thus the transistor is likely to have normally-on characteristics. This is because a donor caused by oxygen vacancies in the metal oxide is generated and the carrier concentration is increased. The transistor having normally-on characteristics causes various problems where malfunction is likely to occur at the time of operation and power consumption is increased at the time of non-operation, for example.

Furthermore, a thermal budget in a step of forming a connection wiring for manufacturing a module causes problems such as degradation of the electrical characteristics of the transistor, such as variations in threshold voltage and an increase in parasitic resistance, and increased variations in electrical characteristics due to the degradation of the electrical characteristics. Since such problems lead directly to a decrease in manufacturing yield, it is important to consider countermeasures. Moreover, the electrical characteristics degrade through a stress test, which can evaluate changes in transistor characteristics due to long-term use (changes over time) in a short time. The degradation of the electrical characteristics is presumably caused by oxygen vacancies in the metal oxide due to high-temperature treatment performed in the manufacturing process or electrical stress applied during the stress test.

In the metal oxide, there is an oxygen atom that has a weak bond to a metal atom and is likely to form an oxygen vacancy. In particular, in the case where the metal oxide is an In—Ga—Zn oxide, a zinc atom and an oxygen atom are likely to form a weak bond (also referred to as a weak Zn—O bond). Here, the weak Zn—O bond means a bond generated between a zinc atom and an oxygen atom, which is weak enough to be broken by high-temperature treatment performed in the manufacturing process or electrical stress applied during the stress test. When a weak Zn—O bond exists in the metal oxide, the bond is broken by heat treatment or current stress, so that an oxygen vacancy is formed. The formation of the oxygen vacancy decreases the stability of the transistor such as resistance to thermal budget and resistance to electrical stress.

A bond generated between an oxygen atom bonded to many zinc atoms and the zinc atoms is a weak Zn—O bond in some cases. A zinc atom is bonded to an oxygen atom more weakly than a gallium atom is. Thus, an oxygen atom bonded to many zinc atoms is likely to form a vacancy. That is, a bond generated between a zinc atom and an oxygen atom is probably weaker than a bond between an oxygen atom and another metal.

In addition, it is probable that a weak Zn—O bond is likely to be formed when impurities exist in the metal oxide. Examples of impurities in the metal oxide include a water molecule and hydrogen. When a water molecule or hydrogen exists in the metal oxide, a hydrogen atom is sometimes bonded to an oxygen atom forming the metal oxide (which is also referred to as an OH bond). In the case where the In—Ga—Zn oxide is single crystal, an oxygen atom forming the metal oxide is bonded to four metal atoms forming the metal oxide. However, an oxygen atom bonded to a hydrogen atom is bonded to two or three metal atoms in some cases. When the number of metal atoms bonded to an oxygen atom decreases, the oxygen atom is likely to form an oxygen vacancy. Note that when a zinc atom is bonded to an oxygen atom that forms an OH bond, the bond between the oxygen atom and the zinc atom is probably weak.

In addition, a weak Zn—O bond is sometimes formed in distortion in a region where a plurality of nanocrystals are connected. Although the shape of nanocrystals is basically a hexagon, they have pentagonal lattice arrangement, heptagonal lattice arrangement, or the like in the distortion. A weak Zn—O bond is formed in the distortion presumably because the bond distances between atoms are not uniform in the distortion.

In addition, it is probable that a weak Zn—O bond is likely to be formed when the crystallinity of the metal oxide is low. When the crystallinity of the metal oxide is high, a zinc atom forming the metal oxide is bonded to four or five oxygen atoms. However, when the crystallinity of the metal oxide becomes lower, the number of oxygen atoms bonded to a zinc atom tends to decrease. When the number of oxygen atoms bonded to a zinc atom decreases, the zinc atom is likely to form a vacancy. That is, a bond generated between a zinc atom and an oxygen atom is presumably weaker than a bond generated in single crystal.

Reducing the number of oxygen atoms and zinc atoms that form the above-described weak Zn—O bonds inhibits formation of oxygen vacancies due to a thermal budget or current stress and can improve the stability of a transistor. Note that in the case where only the number of oxygen atoms that form the weak Zn—O bonds is reduced and the number of zinc atoms that form the weak Zn—O bonds is not reduced, a weak Zn—O bond is sometimes formed again when an oxygen atom is supplied to the vicinity of the zinc atoms. Therefore, it is preferable to reduce the number of zinc atoms and oxygen atoms that form the weak Zn—O bonds.

As a method for reducing the number of oxygen atoms and zinc atoms that form the weak Zn—O bonds, a method in which vacuum baking is performed after a metal oxide is deposited can be given. Vacuum baking is heat treatment performed in a vacuum atmosphere. A vacuum atmosphere is kept by evacuation with a turbomolecular pump or the like. Note that pressure in a treatment chamber is lower than or equal to 1×10⁻² Pa, preferably lower than or equal to 1×10⁻³ Pa. In addition, the substrate temperature in the heat treatment is higher than or equal to 300° C., preferably higher than or equal to 400° C.

Performing the vacuum baking can reduce the number of oxygen atoms and zinc atoms that form the weak Zn—O bonds. Furthermore, since the metal oxide is heated by the vacuum baking, atoms included in the metal oxide are rearranged after the number of oxygen atoms and zinc atoms that form the weak Zn—O bonds is reduced, so that the number of oxygen atoms each bonded to four metal atoms is increased. Consequently, the number of oxygen atoms and zinc atoms that form the weak Zn—O bonds can be reduced, and a weak Zn—O bond can be inhibited from being formed again.

In addition, when impurities exist in the metal oxide, performing the vacuum baking can release water molecules or hydrogen in the metal oxide and reduce the number of OH bonds. When the number of OH bonds in the metal oxide decreases, the proportion of the oxygen atoms each bonded to four metal atoms increases. Furthermore, the atoms forming the metal oxide are rearranged when water molecules or hydrogen is released, so that the number of oxygen atoms each bonded to four metal atoms increases. Thus, a weak Zn—O bond can be inhibited from being formed again.

As described above, when vacuum baking is performed after the metal oxide is deposited, the number of oxygen atoms and zinc atoms that form weak Zn—O bonds can be reduced. Thus, the stability of the transistor can be improved through the step. Furthermore, an improvement in stability of the transistor increases the degree of freedom in selecting materials and formation methods.

<Method for Manufacturing Semiconductor Device>

Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention shown in FIG. 1 is described with reference to FIG. 5 to FIG. 14. In FIG. 5 to FIG. 14, (A) in each drawing is a top view. Furthermore, (B) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Moreover, (C) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Furthermore, (D) of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A5-A6 in (A). Note that for clarity of the drawing, some components are not shown in the top view of (A) in each drawing.

First, a substrate (not shown) is prepared, and the insulator 214 is deposited over the substrate. The insulator 214 can be deposited by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD (Atomic Layer Deposition) method, or the like.

Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD methods can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas to be used.

By a plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Furthermore, a thermal CVD method is a deposition method that does not use plasma and thus enables less plasma damage to an object to be processed. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like), or the like included in a semiconductor device might be charged up by receiving electric charge from plasma. In that case, accumulated electric charge might break the wiring, the electrode, the element, or the like included in the semiconductor device. In contrast, such plasma damage does not occur in the case of a thermal CVD method that does not use plasma, and thus the yield of the semiconductor device can be increased. In addition, the thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

In addition, in an ALD method, one atomic layer can be deposited at a time using self-regulating characteristics of atoms. Thus, the ALD method has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with good coverage, and low-temperature deposition. Furthermore, the ALD method includes a plasma enhanced ALD (PEALD) method that is a deposition method using plasma. The use of plasma is sometimes preferable because deposition at lower temperature is possible. Note that a precursor used in the ALD method sometimes contains impurities such as carbon. Thus, in some cases, a film provided by the ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by X-ray photoelectron spectroscopy (XPS).

Unlike a film formation method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method are film formation methods in which a film is formed by reaction at a surface of an object. Thus, a CVD method and an ALD method are film formation methods that enable favorable step coverage almost regardless of the shape of an object. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity and can be favorably used to cover a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate, and thus is preferably used in combination with another film formation method with a high deposition rate, such as a CVD method, in some cases.

When a CVD method or an ALD method is used, the composition of a film to be formed can be controlled with a flow rate ratio of source gases. For example, by a CVD method or an ALD method, a film with a certain composition can be formed depending on the flow rate ratio of the source gases. Moreover, with a CVD method or an ALD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case of depositing a film while changing the flow rate ratio of source gases, as compared with the case of depositing a film with use of a plurality of deposition chambers, time taken for the deposition can be shortened because time taken for transfer and pressure adjustment is not required. Thus, the productivity of the semiconductor device can be increased in some cases.

In this embodiment, for the insulator 214, aluminum oxide is deposited by a sputtering method. In addition, the insulator 214 may have a multilayer structure. For example, a structure may be employed in which aluminum oxide is deposited by a sputtering method and aluminum oxide is deposited over the aluminum oxide by an ALD method. Alternatively, a structure may be employed in which aluminum oxide is deposited by an ALD method and aluminum oxide is deposited over the aluminum oxide by a sputtering method.

Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator 216, silicon oxide is deposited by a CVD method.

Then, an opening reaching the insulator 214 is formed in the insulator 216 by a lithography method. Note that examples of the opening include a groove and a slit. A region where the opening is formed may be referred to as an opening portion. A wet etching method may be used for the formation of the opening; however, a dry etching method is preferable for microfabrication. As the insulator 214, it is preferable to select an insulator that functions as an etching stopper used in forming the opening by etching the insulator 216. For example, in the case where silicon oxide is used for the insulator 216 in which the opening is to be formed, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214, which is an insulator functioning as an etching stopper.

Note that in the lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developer, so that a resist mask is formed. Then, etching treatment through the resist mask is performed, so that a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed by, for example, exposure of the resist to light such as KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be employed in which a gap between a substrate and a projection lens is filled with liquid (e.g., water) in light exposure. Alternatively, an electron beam or an ion beam may be used instead of the light. Note that a mask is unnecessary in the case of using an electron beam or an ion beam. Note that for removal of the resist mask, dry etching treatment such as ashing can be performed, wet etching treatment can be performed, wet etching treatment can be performed after dry etching treatment, or dry etching treatment can be performed after wet etching treatment.

In addition, a hard mask formed of an insulator or a conductor may be used instead of the resist mask. In the case where a hard mask is used, a hard mask with a desired shape can be formed by forming an insulating film or a conductive film to be a hard mask material over the insulating film to be the insulator 216, forming a resist mask thereover, and then etching the hard mask material. The etching of the insulating film to be the insulator 216 may be performed after removal of the resist mask or with the resist mask remaining. In the latter case, the resist mask sometimes disappears during the etching. The hard mask may be removed by etching after the etching of the insulating film to be the insulator 216. Meanwhile, the hard mask is not necessarily removed when the hard mask material does not affect a post-process or can be utilized in the post-process.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel plate electrodes may have a structure in which a high-frequency power is applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which different high-frequency powers are applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency powers with the same frequency are applied to the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency powers with different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used, for example.

After the formation of the opening, a conductive film to be the first conductor of the conductor 205 is deposited. The conductive film is preferably a conductive barrier film having a function of inhibiting the passage of impurities or oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the first conductor of the conductor 205 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductive film to be the first conductor of the conductor 205, tantalum nitride or a film of tantalum nitride and titanium nitride stacked thereover is deposited. With the use of such a metal nitride as the first conductor of the conductor 205, even when a metal that is easy to diffuse, such as copper, is used for the second conductor of the conductor 205, the metal can be inhibited from being diffused outward through the first conductor of the conductor 205.

Next, a conductive film to be the second conductor of the conductor 205 is deposited over the conductive film to be the first conductor of the conductor 205. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as tungsten, copper, or aluminum is deposited for the conductive film to be the second conductor of the conductor 205.

Next, chemical mechanical polishing (CMP) treatment is performed to remove part of the conductive film to be the first conductor of the conductor 205 and part of the conductive film to be the second conductor of the conductor 205 to expose the insulator 216. As a result, the conductive film to be the first conductor of the conductor 205 and the conductive film to be the second conductor of the conductor 205 remain only in the opening portion. Thus, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205, which has a flat top surface, can be formed (see FIG. 5). Note that the insulator 216 is partly removed by the CMP treatment in some cases.

Note that the method for manufacturing the insulator 216 and the conductor 205 is not limited to the above. For example, a conductive film to be the conductor 205 is formed over the insulator 214 and the conductive film is processed by a lithography method to form the conductor 205. Next, an insulating film to be the insulator 216 may be formed to cover the conductor 205, and part of the insulating film may be removed by CMP treatment until part of the conductor 205 is exposed, so that the conductor 205 and the insulator 216 may be formed.

The conductor 205 and the insulator 216 are formed by CMP treatment as described above, whereby the planarity of the top surfaces of the conductor 205 and the insulator 216 can be improved, and the crystallinity of the CAAC-OS, which is to be the oxide 230 a, the oxide 230 b, and the oxide 230 c in a later process, can be improved.

Next, the insulator 222 is deposited over the insulator 216 and the conductor 205. An insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited as the insulator 222. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in components provided around the transistor 200 are inhibited from being diffused into the transistor 200 through the insulator 222, and generation of oxygen vacancies in the oxide 230 can be inhibited.

The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, heat treatment is preferably performed. The heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., further preferably higher than or equal to 320° C. and lower than or equal to 450° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. Alternatively, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed by performing heat treatment in a nitrogen or inert gas atmosphere and then performing heat treatment in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for released oxygen.

In this embodiment, as the heat treatment, treatment is performed at 400° C. in a nitrogen atmosphere for 1 hour after deposition of the insulator 224. By the heat treatment, impurities such as water or hydrogen contained in the insulator 224 can be removed, for example. The heat treatment can also be performed after the deposition of the insulator 222, for example.

Here, in order to form an excess-oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, an apparatus including a power source for generating high-density plasma using microwaves is preferably used, for example. Alternatively, a power source for applying an RF (Radio Frequency) to a substrate side may be included. The use of high-density plasma enables high-density oxygen radicals to be produced, and RF application to the substrate side allows the oxygen radicals produced by the high-density plasma to be efficiently introduced into the insulator 224. Alternatively, after plasma treatment containing an inert gas is performed with this apparatus, plasma treatment containing oxygen may be performed to compensate for released oxygen. Note that impurities such as water or hydrogen contained in the insulator 224 can be removed by selecting the conditions for the plasma treatment as appropriate. In that case, the heat treatment does not need to be performed.

Next, an oxide film 230A and an oxide film 230B are deposited in this order over the insulator 224 (see FIG. 5). Note that the oxide films are preferably formed successively without exposure to the air. By the deposition without exposure to the air, impurities or moisture from the atmospheric environment can be prevented from being attached onto the oxide film 230A and the oxide film 230B, so that the vicinity of an interface between the oxide film 230A and the oxide film 230B can be kept clean.

The oxide film 230A and the oxide film 230B can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the case where the oxide film 230A and the oxide film 230B are deposited by a sputtering method, for example, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. Increasing the proportion of oxygen contained in the sputtering gas can increase the amount of excess oxygen in the deposited oxide films. In the case where the above oxide films are deposited by a sputtering method, the above In-M-Zn oxide target or the like can be used. Furthermore, a direct current (DC) power source or an alternating current (AC) power source such as a radio frequency (RF) power source is connected to a target, and required power can be applied depending on the electric conductivity of the target.

In particular, part of oxygen contained in the sputtering gas is supplied to the insulator 224 during the deposition of the oxide film 230A in some cases. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A is higher than or equal to 70%, preferably higher than or equal to 80%, further preferably 100%.

In addition, in the case where the oxide film 230B is formed by a sputtering method, when the proportion of oxygen contained in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20% during the deposition, an oxygen-deficient oxide semiconductor is formed. In a transistor in which an oxygen-deficient oxide semiconductor is used for its channel formation region, comparatively high field-effect mobility can be obtained. Furthermore, when deposition is performed while the substrate is heated, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited thereto. In the case where the oxide film to be the oxide 230 b is formed by a sputtering method and the proportion of oxygen contained in the sputtering gas for deposition is higher than 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, an oxygen-excess oxide semiconductor is formed. In a transistor using an oxygen-excess oxide semiconductor for its channel formation region, relatively high reliability can be obtained.

In this embodiment, the oxide film 230A is deposited by a sputtering method using a target with In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or 1:3:4 [atomic ratio]. In addition, the oxide film 230B is deposited by a sputtering method using a target with In:Ga:Zn=4:2:4.1 [atomic ratio]. Note that each of the oxide films is formed to have characteristics required for the oxide 230 by selecting the deposition condition and the atomic ratio as appropriate.

Here, the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are preferably formed without exposure to the air. For example, a multi-chamber deposition apparatus may be used.

Next, heat treatment may be performed. For the heat treatment, the conditions for the above heat treatment can be used. Through the heat treatment, impurities such as water or hydrogen in the oxide film 230A and the oxide film 230B can be removed, for example. In this embodiment, treatment is performed at 400° C. in a nitrogen atmosphere for 1 hour, and treatment is successively performed at 400° C. in an oxygen atmosphere for 1 hour.

Next, the oxide film 230A and the oxide film 230B are processed into island shapes to form the oxide 230 a and the oxide 230 b (see FIG. 6). Note that in this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230 a is reduced in some cases. In this step, the insulator 224 may be processed into an island shape so as to overlap with the oxide 230 a, so that part of the insulator 222 is exposed.

Here, the oxide 230 a and the oxide 230 b are formed to at least partly overlap the conductor 205. Alternatively, a structure may be employed in which an angle formed by the side surfaces of the oxide 230 a and the oxide 230 b and the top surface of the insulator 222 is a small angle. In that case, the angle formed by the side surfaces of the oxide 230 a and the oxide 230 b and the top surface of the insulator 222 is preferably greater than or equal to 60° and less than 70°. With such a shape, coverage with the insulator 256 and the like can be improved in a later step, so that defects such as voids can be reduced. Alternatively, a side surface of the oxide 230 b may be substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230 a and the oxide 230 b are substantially perpendicular to the top surface of the insulator 222, the plurality of transistors 200 can be provided in a smaller area and at a higher density.

There are curved surfaces between the side surfaces of the oxide 230 b and the top surface of the oxide 230 b. That is, an end portion of the side surfaces and an end portion of the top surface are preferably curved (such shapes are hereinafter also referred to as rounded shapes). The radius of curvature of the curved surfaces at an end portion of the oxide 230 b layer is greater than or equal to 3 nm and less than or equal to 10 nm, preferably greater than or equal to 5 nm and less than or equal to 6 nm, for example. When the end portions are not angular, coverage with films in a later deposition process can be improved.

Note that the oxide film 230A and the oxide film 230B may be processed by a lithography method. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by a dry etching method is suitable for microfabrication.

In addition, in some cases, the treatment such as dry etching causes attachment or diffusion of impurities due to an etching gas or the like to a surface or an inside of the oxide 230 a, the oxide 230 b, or the like. Examples of the impurities include fluorine and chlorine.

In order to remove the impurities and the like, cleaning is performed. Examples of a cleaning method include wet cleaning using a cleaning solution or the like, plasma treatment using plasma, and cleaning by heat treatment, and these cleanings may be performed in appropriate combination.

As the wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting an oxalic acid, a phosphoric acid, a hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, the ultrasonic cleaning using pure water or carbonated water is performed.

Then, heat treatment may be performed. For the conditions of the heat treatment, the conditions for the above heat treatment can be used. The heat treatment is preferably performed before the deposition of an insulating film 256A. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C., and may be performed at 200° C., for example. Alternatively, the heat treatment is preferably performed at the same temperature as the deposition temperature of the insulating film 256A. Here, the deposition temperature is not limited to the substrate temperature during the deposition, and includes the set temperature of the deposition apparatus. For example, in the case where the insulating film 256A is deposited at 200° C., the heat treatment is preferably performed at 200° C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. A vacuum atmosphere is kept by evacuation with a turbomolecular pump or the like. Pressure in a vacuum atmosphere of the treatment chamber is lower than or equal to 1×10⁻² Pa, preferably lower than or equal to 1×10⁻³ Pa.

Next, the insulating film 256A is formed so as to cover the oxide 230 a and the oxide 230 b (see FIG. 6). The insulating film 256A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For the insulating film 256A, an insulating film having a function of inhibiting diffusion of oxygen and impurities such as hydrogen is preferably used. For example, an aluminum oxide film is preferably deposited by a sputtering method. When an aluminum oxide film is deposited by a sputtering method using a gas containing oxygen, oxygen can be injected into the insulator 224. That is, the insulator 224 can contain excess oxygen. For the insulating film 256A, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an insulator containing aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like can be used.

Alternatively, aluminum oxide may be deposited for the insulating film 256A while the substrate is heated at a high temperature. The substrate heating temperature during the deposition of the insulating film 256A is higher than or equal to 200° C., preferably higher than or equal to 250° C., further preferably higher than or equal to 350° C.

Alternatively, the insulating film 256A may have a stacked-layer structure.

Next, a dummy gate film to serve as a dummy gate 262A is formed over the insulating film 256A.

The dummy gate film to be the dummy gate 262A is processed to be used as a dummy gate. The dummy gate is an interim gate electrode. That is, the dummy gate film to be the dummy gate 262A is processed to form an interim gate electrode, the dummy gate is removed in a later step, and a gate electrode is formed using a conductive film or the like instead. Thus, a film that is easily processed minutely and easily removed is preferably used as the dummy gate film to be the dummy gate layer 262A.

The dummy gate film to be the dummy gate layer 262A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An insulator, a semiconductor, or a conductor can be used, for example. Specifically, silicon such as polysilicon, microcrystalline silicon, or amorphous silicon, or a metal film of aluminum, titanium, tungsten, or the like is used, for example. Alternatively, a film containing carbon, SOG (Spin On Glass), a resin film, or the like may be formed by a coating method. For example, a photoresist, polyester, polyolefin, polyamide (nylon, aramid, or the like), polyimide, polycarbonate, acrylic, or the like can be given. When SOG or the resin film is formed by a coating method, a surface of the dummy gate film can be made flat. When the surface of the dummy gate film is made flat in this manner, the dummy gate film can be easily processed minutely and easily removed.

The dummy gate needs to protect the oxide 230 from the dopant in the dopant addition described later. Therefore, the dummy gate film to be the dummy gate 262A preferably has sufficient hardness. For the dummy gate film, for example, a film containing carbon is preferable.

In addition, the dummy gate film to be the dummy gate layer 262A can be a multilayer film using different kinds of films. For example, the dummy gate film to be the dummy gate layer 262A can have a two-layer structure in which a conductive film and a resin film over the conductive film are formed. When the dummy gate film has such a structure, the conductive film functions as a stopper film for CMP treatment in a later CMP process in some cases, for example. Alternatively, the end point of the CMP treatment can be detected in some cases, so that processing variations can be reduced in some cases.

Then, the dummy gate film to be the dummy gate layer 262A is etched by a lithography method, so that the dummy gate layer 262A is formed (see FIG. 7). The dummy gate layer 262A is formed to at least partly overlap the conductor 205 and the oxide 230.

After the dummy gate 262A is formed, heat treatment may be performed so that the dummy gate 262A is hardened. In particular, when the shape of the dummy gate 262A is made to have a high aspect ratio, the dummy gate 262A is hardened, so that change in the shape of the dummy gate 262A can be prevented.

Next, a dopant 257 is added to the oxide 230 b with the use of the dummy gate 262A as a mask (see FIG. 7). Accordingly, the layer 253 a and the layer 253 b including the dopant 257 are formed in the regions of the oxide 230 b which do not overlap with the dummy gate 262A. In this manner, the distance between the layer 253 a and the layer 253 b can be controlled through the length of the dummy gate 262A in the channel length direction.

As a method for adding a dopant 257, an ion implantation method in which an ionized source gas is subjected to mass separation and then added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. In the case of performing mass separation, an ion species to be added and its concentration can be adjusted precisely. On the other hand, in the case of not performing mass separation, ions at a high concentration can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that a dopant may be referred to as an ion, donor, acceptor, impurity, element, or the like.

As the dopant 257, an element that forms the oxygen vacancy, an element that is bonded to the oxygen vacancy, or the like is used. Typical examples of the element include boron and phosphorus. Hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas element, or the like can also be used. Typical examples of the rare gas include helium, neon, argon, krypton, and xenon. Furthermore, any one or more metal elements selected from metal elements such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum may be added. Among the above, boron and phosphorus are preferable as the dopant 257. In the case where boron or phosphorus is used as the dopant 257, manufacturing line apparatuses for amorphous silicon or low-temperature polysilicon can be used; thus, capital investment can be reduced.

In particular, an element that easily forms an oxide is preferably used for the dopant 257. Typical examples of the element include boron, phosphorus, aluminum, and magnesium.

A gas containing the impurity element can be used as a source gas for adding the dopant 257. In the case where boron is supplied, typically, a B₂H₆ gas, a BF₃ gas, or the like can be used. In the case where phosphorus is supplied, typically, a PH₃ gas can be used. A mixed gas in which any of these source gases is diluted with a rare gas may be used.

Besides, any of CH₄, N₂, NH₃, AlH₃, AlCl₃, SiH₄, Si₂H₆, F₂, HF, H₂, a rare gas, and the like can be used as the source gas. The ion source is not limited to a gas; a vaporized liquid or a vaporized solid may be used for the ion source.

The addition of the dopant 257 can be controlled by setting the conditions such as the acceleration voltage and the dose in consideration of the composition, the density, the thickness, and the like of the insulating film 256A and the oxide 230 b. In particular, it is preferable that sufficient energy be applied so that the dopant 257 can penetrate the portion of the insulating film 256A which is not in contact with the dummy gate 262A.

The addition amount of the dopant 257 is preferably larger than that of a dopant 258, which will be described later. Thus, the layer 253 which has a higher concentration of the injected element than the layer 252 can be formed. The dopant 257 may be added at an acceleration voltage higher than that for the dopant 258. Thus, the layer 253 in which the element is distributed deeply than in the layer 252 can be formed.

Although the dopant 257 is added substantially perpendicularly to the top surface of the insulator 214 in FIG. 7, one embodiment of the present invention is not limited thereto. The dopant 257 may be added obliquely to the top surface of the insulator 214. By means of the oblique addition of the dopant to the top surface of the insulator 214, the layer 253 a and the layer 253 b can be easily formed in part of the region overlapping with the dummy gate 262A.

In the forming method in this embodiment, the dopant 257 is added to the oxide 230 through the insulating film 256A. With the forming method, the dopant 257 is also added to the insulating film 256A. That is, both the oxide 230 and the insulating film 256A contain the element contained in the dopant 257. In the case where the insulating film 256A contains excess oxygen, the dopant 257 can inhibit diffusion of the excess oxygen to the outside in some cases. Furthermore, the dopant 257 is sometimes added to the oxide 230 a, the insulator 224, and the insulator 222 provided under the oxide 230 b and the insulating film 256A. Thus, the oxide 230 a, the insulator 224, and the insulator 222 may contain the element included in the dopant 257.

Next, the dummy gate 262A is partly removed (hereinafter referred to as slimming process in some cases), and a dummy gate 262B is formed (see FIG. 8). The dummy gate 262B has a shape like a reduced shape of the dummy gate 262A. Thus, as shown in FIG. 8(B), part of the region of the oxide 230 b where the layer 253 is not formed can be exposed from the dummy gate 262B. The part of the region of the oxide 230 b where the layer 253 is not formed becomes the layer 252 in a later step in which the dopant 258 is added. In other words, the region of the oxide 230 b which overlaps with the dummy gate 262B becomes the region 234 that serves as a channel formation region.

As the slimming process, an ashing process in which oxygen in a radical state (an oxygen radical) is used can be employed, for example. However, the slimming process is not limited to the above ashing process as long as the dummy gate 262A can be processed into a finer pattern. For example, plasma treatment or heat treatment under an atmosphere containing oxygen, irradiation treatment with ultraviolet light in a state exposed under an atmosphere of ozone, dry etching treatment, or wet etching treatment can be employed. Note that the channel length of the transistor 200 is determined by the dummy gate 262B; thus, it is preferable that treatment with good controllability is applied to the slimming process.

Through the slimming process, the length of the dummy gate 262A in the A1-A2 direction can be reduced below the resolution limit of a light exposure apparatus, e.g., to less than or equal to ½, preferably less than or equal to ⅓ of the resolution limit. Thus, for example, the channel length of the transistor 200 can be greater than or equal to 1 nm and less than or equal to 60 nm, more preferably greater than or equal to 15 nm and less than or equal to 40 nm. By making the channel length short in such a manner, the transistor 200 can have a high on-state current, a favorable S-value, and higher frequency characteristics.

Next, the dopant 258 is added to the oxide 230 b with the use of the dummy gate 262B as a mask (see FIG. 9). Accordingly, the layer 252 a and the layer 252 b which contain the dopant 258 are formed in the region of the oxide 230 b which does not overlap with the dummy gate 262B and in which the layer 253 is not formed. As described above, the distance between the layer 252 a and the layer 252 b, that is, the channel length of the transistor 200 can be controlled through the width of the dummy gate 262B in the A1-A2 direction.

A similar method to the addition method of the dopant 257 can be employed for adding the dopant 258. At this time, sufficient energy is preferably applied so that the dopant 258 can penetrate the portion of the insulating film 256A which is not in contact with the dummy gate 262B. As the dopant 258, like the dopant 257, the element that forms an oxygen vacancy, the element that is bonded to an oxygen vacancy, or the like is used. Note that the addition amount of the dopant 258 is preferably smaller than the addition amount of the dopant 257.

Although the dopant 258 is added substantially perpendicularly to the top surface of the insulator 214 in FIG. 9, one embodiment of the present invention is not limited thereto. The dopant 258 may be added obliquely to the top surface of the insulator 214. By means of the oblique addition of the dopant to the top surface of the insulator 214, the layer 252 a and the layer 252 b can be formed in part of the region overlapping with the dummy gate 262B in some cases.

In the forming method in this embodiment, the dopant 258 is added to the oxide 230 through the insulating film 256A. Through the manufacturing method, the dopant 258 is also added to the insulating film 256A. That is, both the oxide 230 b and the insulating film 256A contain an element contained in the dopant 258. In the case where the insulating film 256A contains excess oxygen, the dopant 258 can inhibit diffusion of excess oxygen to the outside in some cases. Since the dopant 258 is also added to the layer 253, the layer 253 contains an element contained in the dopant 258 in some cases. Furthermore, the dopant 258 is sometimes added to the oxide 230 a, the insulator 224, and the insulator 222 provided under the oxide 230 b and the insulating film 256A. Thus, the oxide 230 a, the insulator 224, and the insulator 222 may contain the element included in the dopant 258.

As described above, the layer 252 and the layer 253 are formed using the dummy gate 262A and the dummy gate 262B as masks, whereby the conductor 260 formed in a later step can be provided in a self-aligned manner between the layer 253 a and the layer 253 b, and can overlap with the layer 252 a and the layer 252 b in a self-aligned manner.

Note that heat treatment may be performed after the dopant 257 or the dopant 258 is added. Through the heat treatment, hydrogen contained in the region 234 functioning as a channel formation region can be trapped by the oxygen vacancy in the layer 253 in some cases. Thus, the transistor 200 can have stable electrical characteristics and increased reliability. The heat treatment may be performed in a later step.

Next, an insulating film 266A is formed to cover the insulating film 256A and the dummy gate 262B (see FIG. 10). The insulating film 266A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulating film 266A, an insulating film having a function of inhibiting diffusion of oxygen and impurities such as hydrogen is preferably used. For example, an aluminum oxide film is preferably deposited by a sputtering method. When an aluminum oxide film is deposited by a sputtering method using a gas containing oxygen, oxygen can be injected into the insulator 224. That is, the insulator 224 can contain excess oxygen.

Alternatively, aluminum oxide may be deposited as the insulating film 266A while the substrate is heated at a high temperature. The substrate heating temperature during the deposition of the insulating film 266A is higher than or equal to 200° C., preferably higher than or equal to 250° C., further preferably higher than or equal to 350° C. In that case, the deposition of aluminum oxide by an ALD method before the deposition of the insulating film 266A can prevent the dummy gate 262B from being deformed when the insulating film 266A is deposited at the above temperature.

In a later step, the dummy gate 262B and part of the insulating film 266A which is in contact with the dummy gate 262B are removed to form the opening 263. In other words, the size of the opening 263 can be controlled through the thickness of the insulating film 266A. Here, the layer 252 and the layer 253 are formed in a self-aligned manner with respect to the position of the dummy gate 262B. The size of the opening 263 can be controlled with the position of the dummy gate 262B as its center. Thus, the conductor 260 can overlap with the layer 252 by making the opening 263 large. In addition, by making the opening 263 large, the conductor 260 can overlap with the layer 253. In such a manner, an offset region is prevented from being formed between the channel formation region and the source region or the drain region in the oxide 230, so that the effective channel length can be inhibited from being longer than the width of the conductor 260. Accordingly, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics. Note that the size of the opening 263, that is, the size of the overlap region of the transistor 200 can be set as appropriate depending on required electrical characteristics for the transistor 200.

Next, an insulating film 280A is formed over the insulating film 256A, the insulating film 266A, and the dummy gate 262B (see FIG. 10). The insulating film 280A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, parts of the insulating film 280A, the insulating film 266A, and the dummy gate 262B are removed until part of the dummy gate 262B is exposed, so that the insulator 280, the insulator 266B, and a dummy gate 262 are formed (see FIG. 11). The insulator 280, the insulator 266B, and the dummy gate 262 are preferably formed by CMP treatment.

In addition, as described above, when the dummy gate 262B has a two-layer structure in which a conductive film and a resin film over the conductive film are formed, for example, in a CMP process, the conductive film functions as a stopper film for CMP treatment in some cases. Alternatively, the end point of the CMP treatment can be detected with the conductive film in some cases, so that variations in the height of the dummy gate 262 can be reduced in some cases. As shown FIG. 11(B), the top surface of the dummy gate 262 is substantially aligned with the top surfaces of the insulator 266B and the insulator 280.

Next, the dummy gate 262 and parts of the insulating film 256A and the insulating film 266A which are exposed from the insulator 280 are removed to form the opening 263 (see FIG. 12). The dummy gate 262, the insulating film 256A, and the insulating film 266A can be removed by wet etching, dry etching, ashing, or the like using the insulator 280 as a mask. Alternatively, a plurality of the above treatments may be performed in appropriate combination. For example, wet etching treatment may be performed after ashing treatment. The removal of part of the insulating film 266A forms the insulator 266, and the removal of part of the insulating film 256A forms the insulator 256. The dummy gate 262, part of the insulating film 256A, and part of the insulating film 266A are removed, so that part of the surface of the oxide 230 b (including the layer 252 and the layer 253) is exposed through the opening 263.

Note that the dummy gate 262 and the part of the insulating film 256A and the part of the insulating film 266A that are exposed from the insulator 280 are not necessarily removed at the same time. For example, the dummy gate 262 and part of the insulating film 266A which is exposed from the insulator 280 may be removed using the insulating film 256A as an etching stopper, and then part of the insulating film 256A which is exposed from the insulator 280 may be removed.

Next, heat treatment may be performed. For the heat treatment, the conditions for the above heat treatment can be used. By the heat treatment, impurities such as water or hydrogen in the oxide 230 a and the oxide 230 b can be removed through the opening 263. For example, the heat treatment may be performed at 600° C. in a nitrogen atmosphere.

Before depositing an oxide film 230C, oxygen may be added to the oxide 230 b and the insulator 280 by one or more methods selected from an ion implantation method, an ion doping method, a plasma treatment method, and a plasma immersion ion implantation method. In that case, the use of an ion implantation method by which an ionized source gas is subjected to mass separation and then added is preferable because oxygen can be added to the oxide 230 b and the insulator 280 with high controllability.

Next, heat treatment is preferably performed before deposition of an oxide film 230C. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C., and may be performed at 200° C., for example. Alternatively, the heat treatment is preferably performed at the same temperature as the deposition temperature of the oxide film 230C. Here, the deposition temperature is not limited to the substrate temperature during the deposition, and includes the set temperature of the deposition apparatus. For example, in the case where the oxide film 230C is deposited at 300° C., the heat treatment is preferably performed at 300° C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. A vacuum atmosphere is kept by evacuation with a turbomolecular pump or the like. Pressure in a vacuum atmosphere of the treatment chamber is lower than or equal to 1×10⁻² Pa, preferably lower than or equal to 1×10⁻³ Pa.

Next, the oxide film 230C is deposited to be embedded in the opening 263 (see FIG. 13). In addition, the oxide film 230C is preferably deposited successively without being exposed to the air after the heat treatment. For example, it is preferable that the heat treatment and the deposition treatment be successively performed in different chambers by using a multi-chamber type deposition apparatus described later, or the like. The treatment can remove impurities such as moisture, hydrogen, or carbon adsorbed onto the surfaces or the like of the oxide 230 a and the oxide 230 b, and can reduce the moisture concentration and hydrogen concentration in the oxide 230 a and the oxide 230 b. An impurity that is removed by the heat treatment includes an impurity having a bond of hydrogen and carbon, an impurity having a bond of hydrogen and oxygen, and the like. Furthermore, it is possible to prevent reentry of impurities such as hydrogen into the oxide 230 by performing heat treatment and deposition successively without exposure to the air.

The oxide film 230C can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An oxide film to be the oxide film 230C is deposited by a method similar to that for the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide film 230C. An In—Ga—Zn oxide or an oxide that does not contain In can be used for the oxide film 230C. As the oxide that does not contain In, a Ga—Zn oxide, gallium oxide, or the like can be used. Alternatively, as the oxide film 230C, a stacked-layer structure of an In—Ga—Zn oxide and an oxide that does not contain In may be used. The oxide film 230C is deposited by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio]. In this embodiment, the oxide film to be the oxide 230 c is deposited as the oxide film 230C by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio].

The oxide film 230C may have a stacked-layer structure of a first oxide film and a second oxide film over the first oxide film; the first oxide film may be formed using a target similar to that used for forming the oxide film 230B, and the second oxide film may be formed using a target similar to the target used for forming the oxide film 230A.

The oxide film 230C is preferably deposited while the substrate is heated. In that case, the substrate temperature is set to be higher than or equal to 300° C., so that oxygen vacancies in the oxide 230 a, the oxide 230 b, and the oxide film 230C can be reduced. In addition, for example, the oxide film 230C may be deposited at the same temperature as the deposition temperature of an insulating film 250A to be described later. Furthermore, when the oxide film 230C is deposited while the substrate is heated in this manner, the crystallinity of the oxide 230 a, the oxide 230 b, and the oxide film 230C can be improved.

In particular, in the deposition of the oxide film 230C, part of oxygen contained in the sputtering gas is supplied to the oxide 230 a and the oxide 230 b, in some cases. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C is higher than or equal to 70%, preferably higher than or equal to 80%, further preferably 100%. Furthermore, when deposition is performed while the substrate is heated, the crystallinity of the oxide film can be improved.

Next, heat treatment is preferably performed before deposition of the insulating film 250A. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C., and may be performed at 200° C., for example. Alternatively, the heat treatment is preferably performed at the same temperature as the deposition temperature of the insulating film 250A. Here, the deposition temperature is not limited to the substrate temperature during the deposition, and includes the set temperature of the deposition apparatus. For example, in the case where the insulating film 250A is deposited at 350° C., the heat treatment is preferably performed at 350° C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. A vacuum atmosphere is kept by evacuation with a turbomolecular pump or the like. Pressure in a vacuum atmosphere of the treatment chamber is lower than or equal to 1×10⁻² Pa, preferably lower than or equal to 1×10⁻³ Pa.

Next, the insulating film 250A is deposited. The insulating film 250A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulating film 250A, silicon oxide, hafnium oxide, gallium oxide, or the like is preferably formed by using an ALD method. For example, a stacked-layer film of silicon oxide and gallium oxide over the silicon oxide is used as the insulating film 250A. Note that the deposition temperature at the time of depositing the insulating film 250A is preferably higher than or equal to 300° C. and lower than 450° C., further preferably higher than or equal to 300° C. and lower than 400° C., particularly preferably approximately 350° C. For example, when the insulating film 250A is deposited at 350° C., an insulator having few impurities can be deposited.

Note that oxygen is excited by microwaves to generate high-density oxygen plasma, and the insulating film 250A is exposed to the oxygen plasma, so that oxygen can be introduced into the insulating film 250A.

Furthermore, heat treatment may be performed. For the heat treatment, the conditions for the above heat treatment can be used. The heat treatment can reduce the moisture concentration and hydrogen concentration in the insulating film 250A.

Next, the conductive film 260Aa and the conductive film 260Ab are deposited (see FIG. 13). The conductive film 260Aa and the conductive film 260Ab can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A CVD method is preferably used, for example. In this embodiment, the conductive film 260Aa is deposited by an ALD method, and the conductive film 260Ab is deposited by a CVD method.

Then, the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, so that the oxide 230 c, the insulator 250, and the conductor 260 (the conductor 260 a and the conductor 260 b) are formed (see FIG. 14).

Next, heat treatment may be performed. For the heat treatment, the conditions for the above heat treatment can be used. The heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 280. Alternatively, the heat treatment is preferably performed before formation of the insulating film to be the insulator 274. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C., and may be performed at 200° C., for example. Alternatively, the heat treatment is preferably performed at the same temperature as the deposition temperature of the insulating film. Here, the deposition temperature is not limited to the substrate temperature during the deposition, and includes the set temperature of the deposition apparatus. For example, in the case where the insulating film is deposited at 250° C., the heat treatment is preferably performed at 250° C. The heat treatment is preferably performed under reduced pressure, and for example, may be performed in a vacuum atmosphere. A vacuum atmosphere is kept by evacuation with a turbomolecular pump or the like. Pressure in a vacuum atmosphere of the treatment chamber is lower than or equal to 1×10⁻² Pa, preferably lower than or equal to 1×10⁻³ Pa.

Next, an insulating film to be the insulator 274 is formed over the insulator 280 (see FIG. 14). The insulating film to be the insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An aluminum oxide film is preferably deposited as the insulating film to be the insulator 274 by a sputtering method, for example. When an aluminum oxide film is deposited by a sputtering method, hydrogen contained in the insulator 280 can be prevented from being diffused into the oxide 230 in some cases.

The insulator 274 may be deposited in an oxygen-containing atmosphere by a sputtering method, whereby oxygen is added to the insulator 280 during the deposition. Although oxygen is added as an oxygen radical here, for example, the state of oxygen at the time of being added is not limited thereto. Oxygen may be added in the state of an oxygen atom, an oxygen ion, or the like. Heat treatment in a later step can diffuse oxygen such that oxygen can be supplied to the oxide 230 effectively.

Note that at the time of the deposition of the insulator 274, substrate heating is preferably performed. The substrate heating is preferably performed at higher than 100° C. and lower than or equal to 300° C. The substrate heating is further preferably performed at higher than or equal to 120° C. and lower than or equal to 250° C. When the substrate temperature is higher than 100° C., water in the oxide 230 can be removed. Furthermore, water can be prevented from adsorbing on the surface of the formed film.

When the transistor 200 is interposed between the insulator 274 and the insulator 222, a large amount of oxygen can be contained in the insulator 280, the insulator 224, and the oxide 230 without outward diffusion of oxygen. Moreover, impurities such as water or hydrogen can be prevented from entering from above the insulator 274 and from below the insulator 222; thus, the impurity concentrations in the insulator 280, the insulator 224, and the oxide 230 can be lowered.

Next, heat treatment may be performed. For the heat treatment, the conditions for the above heat treatment can be used. The heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 280. Furthermore, by the heat treatment, oxygen contained in the insulator 280 can be diffused.

As described above, since the insulator 256 and the insulator 266 are provided to cover the oxide 230 b in this embodiment, oxygen added to the insulator 280 in the heat treatment does not directly enter the oxide 230 b. Since the insulator 274 is provided in contact with the top surfaces of the conductor 260 and the insulator 280, oxygen added to the insulator 280 in the heat treatment does not diffuse outward. Oxygen added to the insulator 280 in the heat treatment may diffuse into the oxide 230 b through the oxide 230 c, which is in contact with a side surface of the insulator 280. In particular, when a CAAC-OS is used for the oxide 230 c, layered crystals in the oxide 230 c might be aligned along a side surface and a bottom surface of the opening 263. Thus, oxygen diffusing into the oxide 230 c may diffuse into the oxide 230 b along the layered crystals.

Note that in the case where substrate heating is performed when the insulator 274 is formed, the substrate heating may diffuse the oxide from the insulator 280 to the oxide 230. In that case, the heat treatment is not necessarily performed.

Although oxygen is added to the insulator 280 at the same time as the formation of the insulator 274 in the above description, this embodiment is not limited thereto. For example, before depositing the insulator 274, oxygen may be supplied to the insulator 280 by one or more methods selected from an ion implantation method, an ion doping method, a plasma treatment method, and a plasma immersion ion implantation method. In that case, the use of an ion implantation method by which an ionized source gas is subjected to mass separation and then added is preferable because oxygen can be added to the insulator 280 with high controllability. Oxygen may be added to the insulator 280 by one or more methods selected from an ion implantation method, an ion doping method, a plasma treatment method, and in addition, a plasma immersion ion implantation method and oxygen may be added at the same time as the formation of the insulator 274.

Next, an insulator to be the insulator 281 may be deposited over the insulator 274. The insulating film to be the insulator 281 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 14).

Then, openings reaching the layer 253 a and the layer 253 b are formed in the insulator 256, the insulator 266, the insulator 280, the insulator 274, and the insulator 281. The openings may be formed by a lithography method.

Next, an insulating film to be the insulator 241 is deposited and the insulating film is subjected to anisotropic etching, so that the insulator 241 is formed. The insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An insulating film having a function of inhibiting the passage of oxygen is preferably used as the insulating film to be the insulator 241. For example, an aluminum oxide film is preferably deposited by an ALD method. Alternatively, a silicon nitride film may be deposited by an ALD method or a CVD method. In the case where a silicon nitride film is formed by an ALD method, a precursor containing silicon and halogen or a precursor of aminosilanes can be used. As the precursor containing silicon and halogen, SiCl₄, SiH₂Cl₂, Si₂Cl₆, Si₃Cl₈, or the like can be used. As the precursor of aminosilanes, monovalent, divalent, or trivalent aminosilanes can be used. As a nitriding gas, ammonia or hydrazine can be used. In addition, for the anisotropic etching, a dry etching method or the like may be employed, for example. When sidewall portions of the openings have such structures, the passage of oxygen from the outside can be inhibited and oxidation of the conductor 240 a and the conductor 240 b to be formed next can be prevented. Furthermore, impurities such as water or hydrogen can be prevented from being diffused from the conductor 240 a and the conductor 240 b to the outside.

Next, a conductive film to be the conductor 240 a and the conductor 240 b is deposited. The conductive film to be the conductor 240 a and the conductor 240 b desirably has a stacked-layer structure that includes a conductor having a function of inhibiting diffusion of impurities such as water or hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film to be the conductor 240 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b, so that the insulator 281 is exposed. As a result, the conductive film remains only in the openings, so that the conductor 240 a and the conductor 240 b having flat top surfaces can be formed (see FIG. 1). Note that the insulator 281 is partly removed by the CMP treatment in some cases.

Through the above process, the semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIG. 5 to FIG. 14, with use of the method for manufacturing the semiconductor device described in this embodiment, the transistor 200 can be manufactured.

According to one embodiment of the present invention, it is possible to provide a semiconductor device with a high on-state current. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with high frequency characteristics. Alternatively, according to one embodiment of the present invention, it is possible to provide a highly reliable semiconductor device. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with favorable electrical characteristics. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with a low off-state current. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, according to one embodiment of the present invention, it is possible to provide a semiconductor device with high productivity.

<Modification Example of Semiconductor Device>

An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in <Structure example of semiconductor device> above and an example of a method for manufacturing the semiconductor device will be described below with reference to FIG. 15 to FIG. 19.

In FIG. 15 to FIG. 19, (A) in each drawing is a top view. Furthermore, (B) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. Moreover, (C) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Furthermore, (D) in each drawing is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A5-A6 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that for clarity of the drawing, some components are not shown in the top view of (A) in each drawing.

Note that in the semiconductor device shown in FIG. 15 to FIG. 19, components having the same functions as the components in the semiconductor device described in <Structure example of semiconductor device> (see FIG. 1) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structure example of semiconductor device> can be used as the constituent materials for the transistor 200.

The transistor 200 shown in FIG. 15 is different from the transistor 200 shown in FIG. 1 in that the insulator 266 is not included, and the insulator 280 and the insulator 256 are in contact with each other.

The semiconductor device shown in FIG. 15 is manufactured by the same method as the semiconductor device shown in FIG. 1 up to the formation of the dummy gate 262B and the addition of the dopant 258. Therefore, the method for manufacturing the semiconductor device in FIG. 5 to FIG. 9 can be referred to.

Next, a film to be a dummy film 267A is formed to cover the insulating film 256A and the dummy gate 262B. The film to be the dummy film 267A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that it is preferable to use a film that can be easily processed minutely and easily removed as the film to be the dummy film 267A because the film to be the dummy film 267A is finally removed. For example, an insulator that can be used for the insulator 266 may be used. Note that the insulator preferably has a sufficiently high etching rate with respect to the insulator 280 and the insulating film 256A when it is removed in a later step.

Next, the film to be the dummy film 267A is subjected to anisotropic etching so that only part in contact with a sidewall of the dummy gate 262B is left, by which the dummy film 267A is formed (see FIG. 16). As the anisotropic etching, a dry etching method is employed, for example.

In a later step, the dummy gate 262B and the dummy film 267A are removed to form the opening 263. In other words, the size of the opening 263 can be controlled through the thickness of the insulating film 267A. Here, the layer 252 and the layer 253 are formed in a self-aligned manner with respect to the position of the dummy gate 262B. The size of the opening 263 can be controlled through the position of the dummy gate 262B as its center. Thus, the conductor 260 can overlap with the layer 252 by making the opening 263 large. In addition, by making the opening 263 large, the conductor 260 can overlap with the layer 253. With such a structure, an offset region is prevented from being formed between the channel formation region and the source region or the drain region in the oxide 230, so that the effective channel length can be inhibited from being longer than the width of the conductor 260. Accordingly, the transistor 200 can have a higher on-state current, a favorable S-value, and higher frequency characteristics. Note that the size of the opening 263, that is, the size of the overlap region of the transistor 200 can be set as appropriate depending on required electrical characteristics for the transistor 200.

Next, the insulating film 280A is deposited over the insulating film 256A, the dummy film 267A, and the dummy gate 262B by treatment similar to that performed in FIG. 10.

Next, treatment similar to that performed in FIG. 11 is performed so that parts of the insulating film 280A, the dummy film 267A, and the dummy gate 262B are removed until part of the dummy gate 262B is exposed, whereby the insulator 280, a dummy film 267, and the dummy gate 262 are formed (see FIG. 17). The insulator 280, the dummy film 267, and the dummy gate 262 are preferably formed by CMP treatment.

Next, the dummy gate 262, the dummy film 267, and part of the insulating film 256A which is exposed from the insulator 280 are removed to form the opening 263 (see FIG. 18). The dummy gate 262, the dummy film 267, and the insulating film 256A can be removed by wet etching, dry etching, ashing, or the like using the insulator 280 as a mask. Alternatively, a plurality of the above treatments may be performed in appropriate combination. For example, wet etching treatment may be performed after ashing treatment. Here, part of the insulating film 256A is removed, whereby the insulator 256 is formed. By removing the dummy gate 262, the dummy film 267, and part of the insulating film 256A, part of the surface of the oxide 230 b (including the layer 252 and the layer 253) is exposed through the opening 263.

Here, it is preferable that the dummy gate 262 and the dummy film 267 be removed using the insulator 280 and the insulating film 256A as etching stoppers, and then part of the insulating film 256A which is exposed from the insulator 280 is removed using the insulator 280 as a mask. By removing the dummy gate 262, the dummy film 267, and part of the insulating film 256A which is exposed from the insulator 280 are removed in such a step, the opening 263 can be formed without excessive etching of a sidewall of the opening 263.

The following steps in the method for manufacturing the semiconductor device shown in FIG. 15 are similar to those in the method for manufacturing the semiconductor device shown in FIG. 1. Therefore, the method for manufacturing the semiconductor device in FIG. 13 and FIG. 14 can be referred to.

The transistor 200 shown in FIG. 19 is different from the transistor 200 shown in FIG. 1 in that the angle formed between the side surfaces of the insulator 256, the insulator 266, and the insulator 280 and the top surface of the oxide 230 b is greater than 90°.

In the description of the manufacturing method of the semiconductor device in FIG. 7, a side surface of the dummy gate 262A is substantially perpendicular to the top surface of the oxide 230 b. In contrast, when the angle formed by the side surface of the dummy gate 262A and the top surface of the oxide 230 b is less than 90°, that is, when the cross-sectional shape of the dummy gate 262A is a forward tapered shape, the cross-sectional shape of the insulator 256, the insulator 266, and the insulator 280 is a reverse tapered shape as shown in FIG. 19. In addition, the cross-sectional shape of the oxide 230 c, the insulator 250, and the conductor 260 is a forward tapered shape.

The structure, method, and the like described above in this embodiment can be used in combination as appropriate with the structures, methods, and the like described in the other embodiments.

Embodiment 2

In this embodiment, one embodiment of a semiconductor device will be described with reference to FIG. 20 and FIG. 21.

[Memory Device 1]

FIG. 20 shows an example of a semiconductor device (a memory device) using a capacitor that is one embodiment of the present invention. In a semiconductor device of one embodiment of the present invention, the transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment or the like can be used as the transistor 200.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a low off-state current; thus, by using the transistor 200 in a memory device, stored data can be retained for a long time. In other words, such a memory device does not require a refresh operation or has extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the memory device.

In the semiconductor device shown in FIG. 20, a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. In addition, a wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. Furthermore, a gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

Furthermore, by arranging the memory devices shown in FIG. 20 in a matrix, a memory cell array can be formed.

<Transistor 300>

The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region and a drain region. The transistor 300 is either a p-channel transistor or an n-channel transistor.

Here, in the transistor 300 shown in FIG. 20, the semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. In addition, the conductor 316 is provided to cover a side surface and a top surface of the semiconductor region 313 with the insulator 315 therebetween. Note that a material adjusting the work function may be used for the conductor 316. Such a transistor 300 is also referred to as a FIN-type transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be included in contact with an upper portion of the convex portion.

Furthermore, although the case where the convex portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

Note that the transistor 300 shown in FIG. 20 is an example and the structure is not limited thereto; a transistor appropriate for a circuit configuration or a driving method is used.

<Capacitor 100>

The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

For example, a conductor 112 and the conductor 110 over a conductor 240 can be formed at the same time. Note that the conductor 112 has a function of a plug or a wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

Although the conductor 112 and the conductor 110 each having a single-layer structure are shown in FIG. 20, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

In addition, the insulator 130 can be provided to have stacked layers or a single layer using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like.

For example, it is preferable to use a stacked-layer structure of a material with high dielectric strength such as silicon oxynitride and a high-permittivity (high-k) material for the insulator 130. In the capacitor 100 having such a structure, sufficient capacitance can be secured because a high-permittivity (high-k) insulator is included, and dielectric strength can be improved because an insulator with high dielectric strength is included, so that the electrostatic breakdown of the capacitor 100 can be inhibited.

Note that examples of the insulator of the high-permittivity (high-k) material (material with high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Meanwhile, examples of the material with high dielectric strength (material with low relative permittivity) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

<Wiring Layer>

Wiring layers provided with an interlayer film, a wiring, a plug, and the like may be provided between the components. In addition, a plurality of wiring layers can be provided in accordance with design. Here, a plurality of conductors having functions of plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and another part of the conductor functions as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked over the transistor 300 as interlayer films. In addition, a conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.

The insulators functioning as interlayer films may also function as planarization films that cover uneven shapes therebelow. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

Similarly, a conductor 218, a conductor included in the transistor 200 (the conductor 205), and the like are embedded in the insulator 210, an insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 has a function of a plug or a wiring that is electrically connected to the capacitor 100 or the transistor 300. In addition, an insulator 150 is provided over the conductor 120 and the insulator 130.

Examples of an insulator that can be used as an interlayer film include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

For example, when a material having low relative permittivity is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

For example, the insulator 150, the insulator 212, the insulator 352, the insulator 354, and the like each preferably include an insulator having low relative permittivity. For example, the insulator preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, or the like), polyimide, polycarbonate, and acrylic.

In addition, it is preferable that one or both of the insulator 130 and the insulator 150 provided over the conductor 112 or the conductor 120 be an insulator or insulators each having resistivity higher than or equal to 1.0×10¹² Ωcm and lower than or equal to 1.0×10¹⁵ Ωcm, preferably higher than or equal to 5.0×10¹² Ωcm and lower than or equal to 1.0×10¹⁴ Ωcm, further preferably higher than or equal to 1.0×10¹³ Ωcm and lower than or equal to 5.0×10¹³ Qcm. One or both of the insulator 130 and the insulator 150 are preferably an insulator or insulators each having resistivity in the above range because the insulator or the insulators can disperse electric charge accumulated between the transistor 200, the transistor 300, the capacitor 100, and wirings such as the conductor 112 and the conductor 120 and can inhibit poor characteristics and electrostatic breakdown of the transistor and a memory device including the transistor due to the electric charge, while maintaining the insulating property. For such an insulator, silicon nitride or silicon nitride oxide can be used.

In addition, as the insulator having resistivity in the above range, the insulator 140 may be provided below the conductor 112. In that case, the insulator 140 is formed over the insulator 281; opening portions are formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 266, the insulator 256, the insulator 224, the insulator 222, and the like; and in the opening portion, the insulator 241, the conductor 240 that is electrically connected to the transistor 200, the conductor 218, and the like are formed. For the insulator 140, a material similar to that of the insulator 130 or the insulator 150 can be used.

Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. Thus, an insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen is used for the insulator 210, the insulator 350, or the like.

For the insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Specifically, for the insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride; or the like can be used.

For the conductor that can be used as a wiring or a plug, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, for the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, or the like, a single layer or stacked layers of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above material can be used. It is particularly preferred to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum; it is particularly preferred to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

<<Wiring or Plug in Layer Provided with Oxide Semiconductor>>

Note that in the case where an oxide semiconductor is used for the transistor 200, an insulator including an excess-oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess-oxygen region and a conductor provided in the insulator including the excess-oxygen region.

For example, the insulator 241 is preferably provided between the insulator 224 and the conductor 240 in FIG. 20. In particular, the insulator 241 is preferably provided in contact with the insulator 222, the insulator 256, and the insulator 266 that sandwich the insulator 224 including the excess-oxygen region. Since the insulator 241 is in contact with the insulator 222, the insulator 256, and the insulator 266, a structure can be employed in which the insulator 224 is sealed by the insulator having a barrier property. Furthermore, it is also preferable that the insulator 241 be in contact with part of the insulator 280 and the insulator 281. When the insulator 241 extends to the insulator 280 and the insulator 281, diffusion of oxygen and impurities can be further inhibited.

That is, when the insulator 241 is provided, absorption of excess oxygen contained in the insulator 224 by the conductor 240 can be inhibited. In addition, when the insulator 241 is included, diffusion of hydrogen, which is an impurity, into the transistor 200 through the conductor 240 can be inhibited.

Note that an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen is preferably used for the insulator 241. For example, aluminum oxide or hafnium oxide is preferably used. Moreover, it is possible to use, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide or silicon nitride oxide, silicon nitride, or the like.

The above is the description of the structure example. With use of the structure, changes in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device using a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor and having a high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[Memory Device 2]

FIG. 21 shows an example of a memory device using the semiconductor device of one embodiment of the present invention. The memory device shown in FIG. 21 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in FIG. 20.

The transistor 400 can control a second gate voltage of the transistor 200. For example, a structure in which a first gate and a second gate of the transistor 400 are diode-connected to a source, and the source of the transistor 400 is connected to the second gate of the transistor 200 is employed. When a negative potential of the second gate of the transistor 200 is held in this structure, a first gate—source voltage and a second gate—source voltage of the transistor 400 are 0 V. In the transistor 400, a drain current when a second gate voltage and a first gate voltage are 0 V is extremely low; thus, the negative potential of the second gate of the transistor 200 can be maintained for a long time even without power supply to the transistor 200 and the transistor 400. Accordingly, the memory device including the transistor 200 and the transistor 400 can retain stored content for a long time.

Hence, in FIG. 21, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In addition, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. Furthermore, a gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. A wiring 1007 is electrically connected to the source of the transistor 400, a wiring 1008 is electrically connected to the first gate of the transistor 400, a wiring 1009 is electrically connected to the second gate of the transistor 400, and a wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

When the memory devices shown in FIG. 21 are arranged in a matrix like the memory device shown in FIG. 20, a memory cell array can be formed. Note that one transistor 400 can control second gate voltages of a plurality of transistors 200. Thus, the number of the transistor 400 to be provided is preferably smaller than the number of the transistor 200 to be provided.

<Transistor 400>

The transistor 400 and the transistor 200 are formed in the same layer and thus can be fabricated in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b) functioning as a first gate electrode; a conductor 405 (a conductor 405 a and a conductor 405 b) functioning as a second gate electrode; the insulator 222, the insulator 224, and an insulator 450 each functioning as a gate insulating layer; an oxide 430 c including a region where a channel is formed; a layer 453 a, an oxide 431 a, and an oxide 431 b which function as sources; a layer 453 b, an oxide 432 a, and an oxide 432 b which function as drains; and a conductor 440 (a conductor 440 a and a conductor 440 b).

In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431 a and the oxide 432 a are in the same layer as the oxide 230 a, and the oxide 431 b and the oxide 432 b are in the same layer as the oxide 230 b. The layer 453 a and the layer 453 b are layers formed in the same process as the layer 253 a and the layer 253 b. The oxide 430 c is in the same layer as the oxide 230 c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260.

Note that components formed in the same layer can be formed at the same time. For example, the oxide 430 c can be formed by processing an oxide film to be the oxide 230 c.

In the oxide 430 c functioning as an active layer of the transistor 400, oxygen vacancies and impurities such as hydrogen or water are reduced, as in the oxide 230 or the like. Accordingly, the threshold voltage of the transistor 400 can be higher than 0 V, an off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely low.

<<Dicing Line>>

A dicing line (also referred to as a scribe line, a dividing line, or a cutting line in some cases) that is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are obtained in a chip form will be described below.

Examples of a dividing method include the case where a groove (a dicing line) for dividing the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices.

Here, for example, as shown in FIG. 21, a region in which the insulator 256 and the insulator 222 are in contact with each other is preferably designed to be the dicing line. That is, an opening is provided in the insulator 224 near the region to be the dicing line that is provided in the outer edge of the transistor 400 and the memory cell including a plurality of transistors 200. The insulator 256 and the insulator 266 are provided to cover a side surface of the insulator 224.

That is, in the opening provided in the insulator 224, the insulator 222 is in contact with the insulator 254. For example, in this instance, the insulator 222 and the insulator 254 may be formed using the same material and the same method. When the insulator 222 and the insulator 254 are formed using the same material and the same method, the adhesion can be increased. For example, an aluminum oxide is preferably used.

With this structure, the insulator 224, the transistor 200, and the transistor 400 can be enclosed with the insulator 222 and the insulator 254. Since the insulator 222 and the insulator 254 have a function of inhibiting diffusion of oxygen, hydrogen, and water even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements in this embodiment to form a plurality of chips, the entry and diffusion of impurities such as hydrogen or water from the direction of a side surface of the divided substrate to the transistor 200 or the transistor 400 can be inhibited.

Furthermore, with this structure, excess oxygen in the insulator 224 can be prevented from being diffused to the outside of the insulator 254 and the insulator 222. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the oxide where the channel of the transistor 200 or the transistor 400 is formed. The oxygen can reduce oxygen vacancies in the oxide where the channel of the transistor 200 or the transistor 400 is formed. Thus, the oxide where the channel of the transistor 200 or the transistor 400 is formed can be an oxide semiconductor having a low density of defect states and stable characteristics. That is, variation in the electrical characteristics of the transistor 200 or the transistor 400 can be reduced and the reliability can be improved.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

Embodiment 3

In this embodiment, a memory device of one embodiment of the present invention including a transistor in which an oxide is used for a semiconductor (hereinafter also referred to as an OS transistor in some cases) and a capacitor (hereinafter, such a memory device is also referred to as an OS memory device in some cases), will be described with reference to FIG. 22 and FIG. 23. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely low, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

<Structure Example of Memory Device>

FIG. 22(A) shows a structure example of the OS memory device. A memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are wirings connected to memory cells included in the memory cell array 1470, which will be described in detail later. An amplified data signal is output to the outside of the memory device 1400 as a digital data signal RDATA through the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

As power supply voltages, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside. In addition, control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes the signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder or the column decoder. CE denotes a chip enable signal, WE denotes a write enable signal, and RE denotes a read enable signal. Signals processed by the control logic circuit 1460 are not limited thereto, and other input signals are processed to generate control signals for the column decoder or the row decoder as necessary.

The memory cell array 1470 includes a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings that connect the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, and the like. Furthermore, the number of wirings that connect the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, and the like.

Note that FIG. 22(A) shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane; however, this embodiment is not limited thereto. For example, as shown in FIG. 22(B), the memory cell array 1470 may be provided over part of the peripheral circuit 1411. For example, a structure may be employed in which a sense amplifier is provided below the memory cell array 1470 to overlap with the memory cell array 1470.

FIG. 23 shows structure examples of a memory cell applicable to the memory cell MC.

[DOSRAM]

FIG. 23(A) to FIG. 23(C) show structure examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 shown in FIG. 23(A) includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (also referred to as a front gate in some cases) and a back gate.

A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA. A second terminal of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The back gate of the transistor M1 is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line.

The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In data writing and reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying a given potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

The memory cell MC is not limited to the memory cell 1471, and its circuit configuration can be changed. For example, in the memory cell MC, the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL as in a memory cell 1472 shown in FIG. 23(B). Alternatively, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, the transistor M1 not including a back gate, as in a memory cell 1473 shown in FIG. 23(C).

In the case where the semiconductor device described in the above embodiment is used in the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. The use of an OS transistor as the transistor M1 enables the leakage current of the transistor M1 to be extremely low. That is, written data can be retained for a long time by using the transistor M1; thus, the frequency of refresh of the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be omitted. In addition, the extremely low leakage current allows multi-level data or analog data to be retained in the memory cell 1471, the memory cell 1472, or the memory cell 1473.

In the DOSRAM, providing a sense amplifier below the memory cell array 1470 so that they overlap each other as described above can shorten the bit line. This reduces the bit line capacity, which reduces the storage capacity of the memory cell.

[NOSRAM]

FIGS. 23(D) to 23(G) show circuit structure examples of a gain-cell memory cell with two transistors and one capacitor. A memory cell 1474 shown in FIG. 23(D) includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 includes a front gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a memory device including a gain-cell memory cell using an OS transistor as the transistor M2 is referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) in some cases.

A first terminal of the transistor M2 is connected to a first terminal of the capacitor CB. A second terminal of the transistor M2 is connected to a wiring WBL. The gate of the transistor M2 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to a wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitor CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. In data writing, data retention, and data reading, a low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying a given potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

The memory cell MC is not limited to the memory cell 1474, and its circuit configuration can be changed as appropriate. For example, as a memory cell 1475 shown in FIG. 23(E), the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell formed of a transistor with a single-gate structure, that is, the transistor M2 that does not have a back gate, as a memory cell 1476 shown in FIG. 23(F). For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as a memory cell 1477 shown in FIG. 23(G).

In the case where the semiconductor device described in the above embodiment is used in the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. When an OS transistor is used as the transistor M2, the leakage current of the transistor M2 can be extremely low. Consequently, written data can be retained for a long time by using the transistor M2; thus, the frequency of refresh of the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be omitted. In addition, the extremely low leakage current allows multi-level data or analog data to be retained in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

Note that the transistor M3 may be a transistor containing silicon in a channel formation region (hereinafter such a transistor is referred to as a Si transistor in some cases). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. A Si transistor has higher field-effect mobility than an OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, the use of a Si transistor as the transistor M3 enables the transistor M2 to be stacked over the transistor M3, in which case the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.

Alternatively, the transistor M3 may be an OS transistor. When OS transistors are used as the transistors M2 and M3, the circuit of the memory cell array 1470 can be formed using only n-channel transistors.

FIG. 23(H) shows an example of a gain-cell memory cell with three transistors and one capacitor. A memory cell 1478 shown in FIG. 23(H) includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as necessary. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor including a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and a gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily include the back gate.

Note that each of the transistors M5 and M6 may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors, in which case the circuit of the memory cell array 1470 can be formed using only n-channel transistors.

In the case where the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. The use of an OS transistor as the transistor M4 achieves the extremely low leakage current of the transistor M4.

Note that the configurations of a peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement and functions of these circuits and the wirings, circuit components, and the like connected to the circuits can be changed, removed, or added as needed.

The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments and the like.

Embodiment 4

In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG. 24. A plurality of circuits (systems) are mounted on the chip 1200. The technology for integrating a plurality of circuits (systems) on one chip is referred to as system on chip (SoC) in some cases.

As shown in FIG. 24(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

A bump (not shown) is provided on the chip 1200, and as shown in FIG. 24(B), the chip 1200 is connected to a first surface of a printed circuit board (PCB) 1201. A plurality of bumps 1202 are provided on the rear surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

Memory devices such as a DRAM 1221 and a flash memory 1222 may be provided over the motherboard 1203. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. For example, the NOSRAM described in the above embodiment can be used as the flash memory 1222.

The CPU 1211 preferably includes a plurality of CPU cores. The GPU 1212 preferably includes a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each include a memory for storing data temporarily. Alternatively, a common memory for the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the NOSRAM or the DOSRAM described above can be used. The GPU 1212 is suitable for parallel computation of a large number of data and thus can be used for image processing and product-sum operation. When an image processing circuit or a product-sum operation circuit using an oxide semiconductor of the present invention is provided in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.

Since the CPU 1211 and the GPU 1212 are provided in the same chip, a wiring between the CPU 1211 and the GPU 1212 can be shortened; accordingly, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories included in the CPU 1211 and the GPU 1212, and transfer of arithmetic operation results from the GPU 1212 to the CPU 1211 after the arithmetic operation in the GPU 1212 can be performed at high speed.

The analog arithmetic unit 1213 includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the analog arithmetic unit 1213 may include the above-described product-sum operation circuit.

The memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as the interface of the flash memory 1222.

The interface 1215 includes an interface circuit to be connected to an external device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). The network circuit 1216 may further include a circuit for network security.

The circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even when the number of circuits needed for the chip 1200 increases, there is no need to increase the number of steps in the manufacturing process; thus, the chip 1200 can be manufactured at low cost.

The motherboard 1203 provided with the PCB 1201 on which the chip 1200 including the GPU 1212 is mounted, the DRAM 1221, and the flash memory 1222 can be referred to as a GPU module 1204.

The GPU module 1204 includes the chip 1200 using the SoC technology, and thus can have a small size. The GPU module 1204 is excellent in image processing, and thus is suitably used in portable electronic devices such as a smartphone, a tablet terminal, a laptop PC, and a portable (mobile) game console. The product-sum operation circuit using the GPU 1212 can implement the arithmetic operation in a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network (DBN), or the like; hence, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.

The structure described in this embodiment can be used in an appropriate combination with the structures described in the other embodiments.

Embodiment 5

In this embodiment, application examples of the memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). FIG. 25 schematically shows some structure examples of removable memory devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example.

FIG. 25(A) is a schematic diagram of a USB memory. A USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is held in the housing 1101. The substrate 1104 is provided with a memory chip 1105 and a controller chip 1106, for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like on the substrate 1104.

FIG. 25(B) is a schematic external diagram of an SD card, and FIG. 25(C) is a schematic diagram of the internal structure of the SD card. An SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is held in the housing 1111. The substrate 1113 is provided with a memory chip 1114 and a controller chip 1115, for example. When the memory chip 1114 is also provided on a back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate 1113. With such a wireless chip, data can be read from and written in the memory chip 1114 by radio communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like on the substrate 1113.

FIG. 25(D) is a schematic external diagram of an SSD, and FIG. 25(E) is a schematic diagram of the internal structure of the SSD. An SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is held in the housing 1151. The substrate 1153 is provided with a memory chip 1154, a memory chip 1155, and a controller chip 1156, for example. The memory chip 1155 is a work memory of the controller chip 1156, and a DOSRAM chip can be used, for example. When the memory chip 1154 is also provided on a back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like on the substrate 1153.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

Embodiment 6

The semiconductor device according to one embodiment of the present invention can be used for a chip or a processor such as a CPU or a GPU. FIG. 26 shows specific examples of electronic devices including processors such as CPUs and GPUs, or chips of one embodiment of the present invention.

<Electronic Device and System>

The GPU or the chip according to one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, a cellular phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with comparatively large screens, such as a television device, a desktop or laptop personal computer, a monitor for a computer or the like, digital signage, and a large game machine like a pachinko machine. In addition, when an integrated circuit or a chip according to one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on the display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device of one embodiment of the present invention may include a sensor (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, current, voltage, power, radioactive rays, flow rate, humidity, a gradient, oscillation, odor, or infrared rays).

The electronic device of one embodiment of the present invention can have a variety of functions. For example, the electronic device can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium. FIG. 26 shows examples of electronic devices.

[Mobile Phone]

FIG. 26A shows a mobile phone (smartphone) which is a type of an information terminal. An information terminal 5500 includes a housing 5510 and a display portion 5511. As input interfaces, a touch panel is provided in the display portion 5511 and a button is provided in the housing 5510.

When the chip of one embodiment of the present invention is applied to the information terminal 5500, the information terminal 5500 can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the content of the conversation on the display portion 5511; an application for recognizing letters, figures, and the like input to the touch panel of the display portion 5511 by a user and displaying them on the display portion 5511; and an application for performing biometric authentication using fingerprints, voice prints, or the like.

[Information Terminal 1]

FIG. 26(B) shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

As the information terminal 5500 described above, when the chip of one embodiment of the present invention is applied to the desktop information terminal 5300, the desktop information terminal 5300 can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with use of the desktop information terminal 5300, novel artificial intelligence can be developed.

Note that in the above description, as examples of the electronic devices, a smartphone and a desktop information terminal are shown in FIG. 26(A) and FIG. 26(B), respectively; however, the electronic devices can be information terminals other than the smartphone and the desktop information terminal. Examples of an information terminal other than the smartphone and the desktop information terminal include a PDA (Personal Digital Assistant), a notebook information terminal, and a workstation.

[Household Appliance]

FIG. 26(C) shows an electric refrigerator-freezer 5800 as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 including artificial intelligence can be achieved. Utilizing the artificial intelligence enables the electric refrigerator-freezer 5800 to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer 5800, expiration dates of the foods, or the like, a function of automatically adjusting temperature to be appropriate for the foods stored in the electric refrigerator-freezer 5800, and the like.

Although the electric refrigerator-freezer is described in this example as a household appliance, examples of other household appliances include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance.

[Game Machines]

FIG. 26(D) illustrates a portable game machine 5200 as an example of a game machine.

The portable game machine 5200 includes a housing 5201, a display portion 5202, a button 5203, and the like.

When the GPU or the chip of one embodiment of the present invention is applied to the portable game machine 5200, the portable game machine 5200 with low power consumption can be achieved. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit, a peripheral circuit, and a module can be reduced.

Furthermore, when the GPU or the chip of one embodiment of the present invention is applied to the portable game machine 5200, the portable game machine 5200 including artificial intelligence can be achieved.

In general, the progress of a game, the actions and words of game characters, and expressions of a phenomenon and the like occurring in the game are determined by the program in the game; however, the use of artificial intelligence in the portable game machine 5200 enables expressions not limited by the game program. For example, it becomes possible to change expressions such as questions posed by the player, the progress of the game, time, and actions and words of game characters.

In addition, when a game requiring a plurality of players is played on the portable game machine 5200, the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent.

Although the portable game machine is shown as an example of a game machine in FIG. 26(D), the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include a home stationary game machine, an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities.

[Moving Vehicle]

The GPU or the chip of one embodiment of the present invention can be applied to an automobile, which is a moving vehicle, and the periphery of a driver's seat in the automobile.

FIG. 26(E1) shows an automobile 5700, which is an example of a moving vehicle, and FIG. 26(E2) is a diagram showing the surroundings of a windshield inside the automobile. FIG. 26(E2) shows a display panel 5701, a display panel 5702, and a display panel 5703 that are attached to a dashboard and a display panel 5704 that is attached to a pillar.

The display panel 5701 to the display panel 5703 can provide a variety of kinds of information by displaying a speedometer, a tachometer, mileage, a fuel gauge, a gear state, air-condition setting, and the like. In addition, the content, layout, or the like of the display on the display panels can be changed as appropriate to suit the user's preference, so that the design quality can be increased. The display panel 5701 to the display panel 5703 can also be used as lighting devices.

The display panel 5704 can compensate for view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not shown) provided for the automobile 5700. That is, displaying an image taken by the imaging device provided outside the automobile 5700 leads to compensation for the blind spot and an increase in safety. In addition, displaying an image to compensate for a portion that cannot be seen makes it possible for the driver to confirm the safety more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied to a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile 5700, for example. The chip can also be used for a navigation system, risk prediction, or the like. A structure may be employed in which the display panel 5701 to the display panel 5704 display navigation information, risk prediction information, or the like.

Note that although an automobile is described above as an example of a moving vehicle, the moving vehicle is not limited to an automobile. Examples of the moving vehicle include a train, a monorail train, a ship, and a flying vehicle (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can each include a system utilizing artificial intelligence when the chip of one embodiment of the present invention is applied to each of these moving vehicles.

[Broadcasting System]

The GPU or the chip of one embodiment of the present invention can be applied to a broadcasting system.

FIG. 26(F) schematically shows data transmission in a broadcasting system.

Specifically, FIG. 26(F) shows a path in which a radio wave (a broadcast signal) transmitted from a broadcast station 5680 is delivered to a television receiver (TV) 5600 of each household. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by an antenna 5650 is transmitted to the TV 5600 through the receiving device.

Although a UHF (Ultra High Frequency) antenna is shown as the antenna 5650 in FIG. 26(F), a BS/110° CS antenna, a CS antenna, or the like can also be used as the antenna 5650.

A radio wave 5675A and a radio wave 5675B are broadcast signals for terrestrial broadcasting; a radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. Each household can view terrestrial TV broadcasting on the TV 5600 by receiving the radio wave 5675B with the antenna 5650. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 26(F) and may be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like.

The broadcasting system may be a broadcasting system utilizing artificial intelligence by applying the chip of one embodiment of the present invention. When broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder. When the antenna 5650 receives the compressed broadcast data, the compressed broadcast data is decompressed by a decoder of the receiving device included in the TV 5600. With use of artificial intelligence, for example, a display pattern included in an image to be displayed can be recognized in motion compensation prediction, which is one of the compression methods for the encoder. In addition, in-frame prediction or the like can also be performed utilizing artificial intelligence. Furthermore, for example, when broadcast data with low resolution is received and the broadcast data is displayed on the TV 5600 with high resolution, image interpolation processing such as upconversion can be performed in the broadcast data decompression by the decoder.

The broadcasting system utilizing artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which needs a larger amount of broadcast data.

In addition, as an application of artificial intelligence in the TV 5600, a recording device including artificial intelligence may be provided in the TV 5600, for example. With such a structure, the artificial intelligence in the recording device can learn the user's preference, so that TV programs that suit the user's preference can be recorded automatically.

The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, their effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

This embodiment can be implemented in combination with any of the structures described in the other embodiments and the like, as appropriate.

REFERENCE NUMERALS

-   200: transistor, 205: conductor, 210: insulator, 212: insulator,     214: insulator, 216: insulator, 218: conductor, 222: insulator, 224:     insulator, 230: oxide, 230 a: oxide, 230A: oxide film, 230 b: oxide,     230B: oxide film, 230 c: oxide, 230 c 1: oxide, 230 c 2: oxide,     230C: oxide film, 231: region, 231 a: region, 231 b: region, 232:     region, 232 a: region, 232 b: region, 234: region, 240: conductor,     240 a: conductor, 240 b: conductor, 241: insulator, 241 a:     insulator, 241 b: insulator, 244: insulator, 250: insulator, 250A:     insulating film, 252: layer, 252 a: layer, 252 b: layer, 253: layer,     253 a: layer, 253 b: layer, 254: insulator, 256: insulator, 256 a:     insulator, 256A: insulating film, 256 b: insulator, 257: dopant,     258: dopant, 260: conductor, 260 a: conductor, 260Aa: conductive     film, 260Ab: conductive film, 260 b: conductor, 262: dummy gate,     262A: dummy gate, 262B: dummy gate, 263: opening, 266: insulator,     266A: insulating film, 266B: insulator, 267: dummy film, 267A: dummy     film, 274: insulator, 274 a: insulator, 274 b: insulator, 280:     insulator, 280A: insulating film, 281: insulator 

1. A semiconductor device comprising: a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a conductor over the first insulator; a second insulator in contact with part of a top surface of the second oxide, part of a side surface of the second oxide, and part of a side surface of the third oxide; a third insulator over the second insulator; and a fourth insulator in contact with a top surface of the third oxide, a top surface of the first insulator, a top surface of the conductor, and a top surface of the third insulator, wherein the second oxide includes a first region, a second region, a third region between the first region and the second region, a fourth region between the first region and the third region, and a fifth region between the second region and the third region, wherein the resistance of the first region and the resistance of the second region are lower than the resistance of the third region, wherein the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region, wherein the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region, wherein part of the third oxide and part of the first insulator are provided between a side surface of the conductor and a side surface of the third insulator, and wherein the second insulator is in contact with the first region and the second region.
 2. The semiconductor device according to claim 1, wherein the conductor overlaps with at least part of the first region and part of the second region.
 3. The semiconductor device according to claim 1, further comprising a fifth insulator in contact with a top surface of the second insulator, wherein the fifth insulator is in contact with a bottom surface of the third insulator and the side surface of the third oxide.
 4. The semiconductor device according to claim 1, wherein the first region, the second region, the fourth region, and the fifth region contain one of phosphorus or boron.
 5. The semiconductor device according to claim 4, wherein the first region and the second region contain phosphorus or boron more than the fourth region and the fifth region.
 6. The semiconductor device according to claim 1, wherein the first region, the second region, the fourth region, and the fifth region contain more oxygen vacancies than the third region.
 7. The semiconductor device according to claim 1, wherein the first region, the second region, the fourth region, and the fifth region contain more hydrogen than the third region.
 8. A method for manufacturing a semiconductor device, comprising: forming a first oxide and a second oxide over the first oxide; forming a first insulating film covering the first oxide and the second oxide; forming a first dummy gate over the first insulating film to overlap with the second oxide; adding a first dopant to the second oxide using the first dummy gate as a mask; forming a second dummy gate by removing part of the first dummy gate; exposing part of the second oxide from the second dummy gate; adding a second dopant to the second oxide using the second dummy gate as a mask; forming a second insulating film covering the first insulating film and the second dummy gate; forming a third insulating film over the second insulating film; removing part of the second insulating film and part of the third insulating film until a top portion of the second dummy gate is exposed; forming an opening by removing the second dummy gate, part of the second insulating film, and part of the first insulating film; forming a third oxide, a fourth insulating film, and a conductive film in this order to be embedded in the opening; and removing part of the third oxide, part of the fourth insulating film, and part of the conductive film until a top portion of the third insulating film is exposed.
 9. The method for manufacturing the semiconductor device, according to claim 8, wherein phosphorus or boron is used for the first dopant and the second dopant.
 10. The method for manufacturing the semiconductor device according to claim 8, wherein the first dopant is added more than the second dopant.
 11. The method for manufacturing the semiconductor device, according to claim 8, wherein the first dopant and the second dopant are added by an ion implantation method or an ion doping method.
 12. The method for manufacturing the semiconductor device, according to claim 8, wherein the first dummy gate contains carbon.
 13. The method for manufacturing the semiconductor device, according to claim 8, wherein the second dummy gate is formed by ashing treatment using an oxygen radical.
 14. A semiconductor device comprising: a first oxide; a second oxide over the first oxide; a third oxide over the second oxide; a first insulator over the third oxide; a conductor over the first insulator; a second insulator in contact with part of a top surface of the second oxide, part of a side surface of the second oxide, and part of a side surface of the third oxide; a third insulator over the second insulator; and a fourth insulator in contact with a top surface of the third oxide, a top surface of the first insulator, a top surface of the conductor, and a top surface of the third insulator, wherein the second oxide includes a first region, a second region, a third region between the first region and the second region, a fourth region between the first region and the third region, and a fifth region between the second region and the third region, wherein the first region, the second region, the fourth region, and the fifth region contain a dopant, wherein the first region and the second region have a higher dopant concentration than the fourth region and the fifth region, wherein the conductor overlaps with the third region, the fourth region, and the fifth region, wherein part of the third oxide and part of the first insulator are provided between a side surface of the conductor and a side surface of the third insulator, and wherein the second insulator is in contact with the first region and the second region. 